GR712RC datasheet(25/48 Pages) AEROFLEX

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AEROFLEX GAISLER

GR712RC-DS

February 2013, Issue 2.0

Table 14. Timing parameters (VDD = 1.8 V +/- 0.15 V, VDDIO = 3.3 V +/- 0.3 V, Tcase = -55˚C to +125˚C)

Name

Parameter

Reference edge 2)

Min

Max

Unit

tFTMCTRL0

address clock to output delay 3)

rising SDCLK edge

0 1)

7.5

tFTMCTRL1

clock to RAMSN[1:0] and

ROMSN[1:0]output delay 3)

rising SDCLK edge

0 1)

7.5

tFTMCTRL1

clock to IOSN output delay 3)

rising SDCLK edge

0 1)

8.5

tFTMCTRL2

clock to output delay

rising SDCLK edge

0 1)

8.5

tFTMCTRL3

clock to data output delay

rising SDCLK edge

0 1)

6.5

tFTMCTRL4

clock to data non-tri-state delay

rising SDCLK edge

0 1)

6.5

tFTMCTRL5

clock to data tri-state delay 4)

rising SDCLK edge

0 1)

6.5 1)

tFTMCTRL6

clock to output delay

rising SDCLK edge

0 1)

8.5

tFTMCTRL7

data input to clock setup

rising SDCLK edge

6.9

tFTMCTRL8

data input from clock hold

rising SDCLK edge

-0.5 1)

tFTMCTRL9

input to clock setup

rising SDCLK edge

6.9

tFTMCTRL10

input from clock hold

rising SDCLK edge

-0.5 1)

Note 1:

Parameter not measured during production test.

Note 2:

The speciﬁed timing is valid for the default programmable internal clock delay of value 0.

Note 3:

The ADDRESS[23:0] and RAMSN[1:0] signals change in the same clock cycle, which might not be

compatible with all SRAM types. Check your SRAM documentation for compatibility.

Note 4:

GR712RC does not provide internal pull-up resistors on the DATA[31:0] and CB[15:0] buses. In the

case of prolonged periods of idle bus activity in a board design, i.e. high impedance state, it is

advised to add external pull-up resistors.

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