AT90USB646 datasheet(178/456 Pages) ATMEL

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178

7593L–AVR–09/12

AT90USB64/128

The dashed boxes in the block diagram separate the three main parts of the USART (listed from

the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.

The Clock Generation logic consists of synchronization logic for external clock input used by

synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is

only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a

serial Shift Register, Parity Generator and Control logic for handling different serial frame for-

mats. The write buffer allows a continuous transfer of data without any delay between frames.

The Receiver is the most complex part of the USART module due to its clock and data recovery

units. The recovery units are used for asynchronous data reception. In addition to the recovery

units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level

receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and

can detect Frame Error, Data OverRun and Parity Errors.

19.2

Clock generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART

Control and Status Register C (UCSRnC) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the

UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register

for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCKn pin is only active when using synchronous mode.

Figure 19-2 shows a block diagram of the clock generation logic.

Figure 19-2. Clock generation logic, block diagram.

Signal description:

txclk

Transmitter clock (Internal Signal).

rxclk

Receiver base clock (Internal Signal).

xcki

Input from XCK pin (internal Signal). Used for synchronous slave

operation.

xcko

Clock output to XCK pin (Internal Signal). Used for synchronous master

operation.

OSC

XTAL pin frequency (System Clock).

Prescaling

down-counter

UBRR

fosc

UBRR+1

Sync

OSC

XCK

txclk

U2X

UMSEL

DDR_XCK

xcki

xcko

DDR_XCK

rxclk

Edge

detector

UCPOL

AT90USB646 Datasheet(PDF) 178 Page - ATMEL Corporation

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