AD7843 datasheet(4/21 Pages) AD

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AD7843

Rev. B | Page 3 of 20

SPECIFICATIONS

VCC = 2.7 V to 3.6 V, VREF = 2.5 V, fSCLK = 2 MHz, TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter

AD7843A1

Unit

Test Conditions/Comments

DC ACCURACY

Resolution

Bits

No Missing Codes

Bits min

Integral Nonlinearity2

±2

LSB max

Offset Error2

±6

LSB max

VCC = 2.7 V

Offset Error Match3

LSB max

0.1

LSB typ

Gain Error2

±4

LSB max

Gain Error Match3

LSB max

0.1

LSB typ

Power Supply Rejection

dB typ

SWITCH DRIVERS

On-Resistance2

Y+, X+

Ω typ

Y−, X−

Ω typ

ANALOG INPUT

Input Voltage Ranges

0 to VREF

DC Leakage Current

±0.1

µA typ

Input Capacitance

pF typ

REFERENCE INPUT

VREF Input Voltage Range

1.0/+VCC

V min/max

DC Leakage Current

±1

µA max

VREF Input Impedance

GΩ typ

CS = GND or +VCC

VREF Input Current3

µA max

8 µA typ

µA typ

fSAMPLE = 12.5 kHz

µA max

CS = +VCC; 0.001 µA typ

LOGIC INPUTS

Input High Voltage, VINH

2.4

V min

Input Low Voltage, VINL

0.4

V max

Input Current, IIN

±1

µA max

Typically 10 nA, VIN = 0 V or +VCC

Input Capacitance, CIN4

pF max

LOGIC OUTPUTS

Output High Voltage, VOH

VCC − 0.2

V min

ISOURCE = 250 µA; VCC = 2.2 V to 5.25 V

Output Low Voltage, VOL

0.4

V max

ISINK = 250 µA

PENIRQ Output Low Voltage, VOL

0.4

V max

ISINK = 250 µA; 100 kW pull-up

Floating-State Leakage Current

±10

µA max

Floating-State Output Capacitance4

pF max

Output Coding

Straight (Natural) Binary

CONVERSION RATE

Conversion Time

DCLK Cycles max

Track-and-Hold Acquisition Time

DCLK Cycles min

Throughput Rate

125

kSPS max

Footnotes on next page.

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