AD7851

–10–

REV. B

AD7851 ON-CHIP REGISTERS

The AD7851 powers up with a set of default conditions, and the user need not ever write to the device. In this case, the AD7851 will

operate as a read-only ADC. The AD7851 still retains the flexibility for performing a full power-down and a full self-calibration.

Note that the DIN pin should be tied to DGND for operating the AD7851 as a read-only ADC.

Extra features and flexibility, such as performing different power-down options, different types of calibrations, including system cali-

bration, and software conversion starts can be selected by writing to the part.

The AD7851 contains a control register, ADC output data register, status register, test register, and 10 calibration registers.

The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration

registers are both read/write registers. The test register is used for testing the part and should not be written to.

Addressing the On-Chip Registers

Writing

A write operation to the AD7851 consists of 16 bits. The two MSBs, ADDR0 and ADDR1, are decoded to determine which regis-

ter is addressed, and the subsequent 14 bits of data are written to the addressed register. It is not until all 16 bits are written that

the data is latched into the addressed register. Table I shows the decoding of the address bits, while Figure 4 shows the overall

write register hierarchy.

Table I. Write Register Addressing

ADDR1

ADDR0

Comment

00

This combination does not address any register so the subsequent 14 data bits are ignored.

01

This combination addresses the TEST REGISTER. The subsequent 14 data bits are written to the test register.

10

This combination addresses the CALIBRATION REGISTERS. The subsequent 14 data bits are written

to the selected calibration register.

11

This combination addresses the CONTROL REGISTER. The subsequent 14 data bits are written to the

control register.

Reading

To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These

bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address

bits while Figure 5 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be

from the ADC output data register.

Once the read selection bits are set in the control register, all subsequent read operations that follow will be from the selected register

until the read selection bits are changed in the control register.

Table II. Read Register Addressing

RDSLT1

RDSLT0

Comment

00

All successive read operations will be from ADC OUTPUT DATA REGISTER. This is the power-up default

setting. There will always be two leading zeros when reading from the ADC output data register.

01All successive read operations will be from TEST REGISTER.

10All successive read operations will be from CALIBRATION REGISTERS.

11All successive read operations will be from STATUS REGISTER.

ADDR1, ADDR0

DECODE

TEST

REGISTER

CONTROL

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

OFFSET (1)

GAIN (1)

01

10

11

00

01

10

11

CALSLT1, CALSLT0

DECODE

CALIBRATION

REGISTERS

Figure 4. Write Register Hierarchy/Address Decoding

RDSLT1, RDSLT0

DECODE

TEST

REGISTER

CALIBRATION

REGISTERS

STATUS

REGISTER

GAIN (1)

OFFSET (1)

DAC (8)

GAIN (1)

OFFSET (1)

OFFSET (1)

GAIN (1)

01

10

11

00

01

10

11

CALSLT1, CALSLT0

DECODE

ADC OUTPUT

DATA REGISTER

00

Figure 5. Read Register Hierarchy/Address Decoding