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AD9726-EBZ Datasheet(PDF) 7 Page - Analog Devices |
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AD9726-EBZ Datasheet(HTML) 7 Page - Analog Devices |
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7 / 24 page ![]() AD9726 Rev. B | Page 7 of 24 CLK+/CLK– IOUTA OR IOUTB tPIPE-BYPASS + tPD-BYPASS DB0 TO DB15 Figure 5. Data Synchronization Bypass Pipeline Delay CSB SCLK SDIO (SD0) tCPWH tDSU tDH tCPWL SCLK SET-UP TIME SDIO SET-UP TIME SDIO HOLD TIME SDIO (SD0) VALID TIME SCLK PULSE WIDTH HIGH/LOW TIME tCSU tDV Figure 6. SPI Timing Diagram |
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