AD9249 datasheet(19/36 Pages) AD

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Data Sheet

AD9249

Rev. 0 | Page 19 of 36

If the internal reference of the AD9249 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 37 shows

how the internal reference voltage is affected by loading.

Figure 37. VREF Error vs. Load Current

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 38 shows the typical drift characteristics of the

internal reference in 1.0 V mode.

Figure 38. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

7.5 kΩ load (see Figure 31). The internal buffer generates the

positive and negative full-scale references for the ADC core.

Therefore, limit the external reference to a maximum of 1.0 V.

Do not leave the SENSE pin floating.

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9249 sample clock inputs,

CLK+ and CLK−, with a differential signal. The signal is typically

ac-coupled into the CLK+ and CLK− pins via a transformer or

capacitors. These pins are biased internally (see Figure 25) and

require no external bias.

Clock Input Options

The AD9249 has a flexible clock input structure. The clock input

can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless

of the type of signal being used, clock source jitter is of the

utmost concern, as described in the Jitter Considerations section.

Figure 39 and Figure 40 show two preferred methods for clocking

the AD9249 (at clock rates of up to 520 MHz prior to the internal

clock divider). A low jitter clock source is converted from a single-

ended signal to a differential signal using either an RF transformer

or an RF balun.

The RF balun configuration is recommended for clock frequencies

from 65 MHz to 520 MHz, and the RF transformer is recom-

mended for clock frequencies from 10 MHz to 200 MHz. The

antiparallel Schottky diodes across the transformer/balun

secondary winding limit clock excursions into the AD9249 to

approximately 0.8 V p-p differential.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9249 while

preserving the fast rise and fall times of the signal that are critical

to achieving a low jitter performance. However, the diode capaci-

tance comes into play at frequencies above 500 MHz. Take care

when choosing the appropriate signal limiting diode.

Figure 39. Transformer-Coupled Differential Clock (Up to 200 MHz)

Figure 40. Balun-Coupled Differential Clock (65 MHz to 520 MHz)

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

3.0

2.5

2.0

1.5

1.0

0.5

LOAD CURRENT (mA)

INTERNAL VREF = 1V

–8

–40

TEMPERATURE (°C)

–6

–4

–2

–15

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR

0.1µF

CLOCK

INPUT

0.1µF

50Ω

CLK–

CLK+

SCHOTTKY

DIODES:

HSMS2822

ADC

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