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Data Sheet

AD9249

Rev. 0 | Page 21 of 36

Treat the clock input as an analog signal in cases where aperture

jitter may affect the dynamic range of the AD9249. Separate the

clock driver power supplies from the ADC output driver supplies

to avoid modulating the clock signal with digital noise. Low jitter,

crystal controlled oscillators are excellent clock sources. If

another type of source generates the clock (by gating, dividing, or

another method), ensure that it is retimed by the original clock

at the last step.

See the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance, and the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter,

for more in depth information about jitter performance as it

relates to ADCs.

POWER DISSIPATION AND POWER-DOWN MODE

As shown in Figure 45, the power dissipated by the AD9249 is

proportional to its sample rate and can be set to one of several

power saving modes using Register 0x100, Bits[2:0].

Figure 45. Total Power vs. fSAMPLE for fIN = 9.7 MHz

The AD9249 is placed in power-down mode either by the SPI

port or by asserting the PDWN pin high. In this state, the ADC

typically dissipates 2 mW. During power-down, the output drivers

are placed in a high impedance state. Asserting the PDWN pin

low returns the AD9249 to its normal operating mode. Note

that PDWN is referenced to the digital output driver supply

(DRVDD) and should not exceed that supply voltage.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. The internal capacitors are discharged when the device

enters power-down mode and then must be recharged when

returning to normal operation. As a result, wake-up time is

related to the time spent in power-down mode, and shorter

power-down cycles result in proportionally shorter wake-up

times. When using the SPI port interface, the user can place the

ADC in power-down mode or standby mode. Standby mode

allows the user to keep the internal reference circuitry powered

when faster wake-up times are required. See the Memory Map

section for more details on using these features.

DIGITAL OUTPUTS AND TIMING

The AD9249 differential outputs conform to the ANSI-644 LVDS

standard on default power-up. This can be changed to a low power,

reduced signal option (similar to the IEEE 1596.3 standard) via

the SPI. The LVDS driver current is derived on chip and sets the

output current at each output equal to a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing (or 700 mV p-p

differential) at the receiver.

When operating in reduced range mode, the output current

reduces to 2 mA. This results in a 200 mV swing (or 400 mV p-p

differential) across a 100 Ω termination at the receiver.

The AD9249 LVDS outputs facilitate interfacing with LVDS

receivers in custom ASICs and FPGAs for superior switching

performance in noisy environments. Single point-to-point net

topologies are recommended with a 100 Ω termination resistor

placed as near to the receiver as possible. If there is no far end

receiver termination or there is poor differential trace routing,

timing errors may result. To avoid such timing errors, it is recom-

mended that the trace length be less than 24 inches, with all traces

the same length. Place the differential output traces as near to each

other as possible. An example of the FCO and data stream with

proper trace length and position is shown in Figure 46. Figure 47

shows an LVDS output timing example in reduced range mode.

Figure 46. LVDS Output Timing Example in ANSI-644 Mode (Default)

Figure 47. LVDS Output Timing Example in Reduced Range Mode

1.0

0.9

0.8

0.7

0.6

0.5

0.4

SAMPLE RATE (MSPS)

50MSPS

SETTING

65MSPS

SETTING

20MSPS

SETTING

40MSPS

SETTING

FCO 500mV/DIV

DCO 500mV/DIV

DATA 500mV/DIV

5ns/DIV

FCO 500mV/DIV

DCO 500mV/DIV

DATA 500mV/DIV

5ns/DIV

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