S25FS-S datasheet(63/154 Pages) SPANSION

63 / 154 page

November 6, 2013 S25FS-S_00_04

S25FS-S Family

Da ta

Shee t

(Prelim i nar y )

8.6.3

Configuration Register 1

Configuration Register 1 controls certain interface and data protection functions. The register bits can be

changed using the WRR command with sixteen input cycles or with the WRAR command.

8.6.3.1

Configuration Register 1 Non-Volatile (CR1NV)

Related Commands: Write Registers (WRR 01h), Read Any Register (RDAR 65h), Write Any Register

(WRAR 71h).

Top or Bottom Protection (TBPROT_O) CR1NV[5]: This bit defines the operation of the Block Protection

bits BP2, BP1, and BP0 in the Status Register. As described in the Status Register section, the BP2-0 bits

allow the user to optionally protect a portion of the array, ranging from 1/64, ¼, ½, etc., up to the entire array.

When TBPROT_O is set to a 0 the Block Protection is defined to start from the top (maximum address) of the

array. When TBPROT_O is set to a 1 the Block Protection is defined to start from the bottom (zero address)

of the array. The TBPROT_O bit is OTP and set to a 0 when shipped from Spansion. If TBPROT_O is

programmed to 1, writing the bit with a 0 does not change the value or set the Program Error bit (P_ERR in

SR1V[6]).

The desired state of TBPROT_O must be selected during the initial configuration of the device during system

manufacture; before the first program or erase operation on the main flash array. TBPROT_O must not be

programmed after programming or erasing is done in the main flash array.

CR1NV[4]: Reserved for Future Use.

Block Protection Non-Volatile (BPNV_O) CR1NV[3]: The BPNV_O bit defines whether the BP_NV 2-0 bits

or the BP 2-0 bits in the Status Register are selected to control the Block Protection feature. The BPNV_O bit

is OTP and cleared to a 0 with the BP_NV bits cleared to “000” when shipped from Spansion. When BPNV_O

is set to a 0 the BP_NV 2-0 bits in the Status Register are selected to control the block protection and are

written by the WRR command. The time required to write the BP_NV bits is tW. When BPNV is set to a 1 the

BP2-0 bits in the Status Register are selected to control the block protection and the BP_NV 2-0 bits will be

programmed to binary “111”. This will cause the BP 2-0 bits to be set to binary 111 after POR, hardware

reset, or command reset. When BPNV is set to a 1, the WRR command writes only the volatile version of the

BP bits (SR1V[4:2]). The non-volatile version of the BP bits (SR1NV[4:2]) are no longer affected by the WRR

command. This allows the BP bits to be written an unlimited number of times because they are volatile and

the time to write the volatile BP bits is the much faster tCS volatile register write time. If BPNV_O is

programmed to 1, writing the bit with a 0 does not change the value or set the Program Error bit (P_ERR in

SR1V[6]).

TBPARM_O CR1NV[2]: TBPARM_O defines the logical location of the parameter block. The parameter

block consists of eight 4-kB parameter sectors, which replace a 32 kB portion of the highest or lowest address

sector. When TBPARM_O is set to a 1 the parameter block is in the top of the memory array address space.

When TBPARM_O is set to a 0 the parameter block is at the Bottom of the array. TBPARM_O is OTP and set

Table 8.17 Configuration Register 1 Non-Volatile (CR1NV)

Bits

Field Name

Function

Type

Default

State

Description

RFU

Reserved for Future

Use

Non-Volatile

Reserved.

RFU

TBPROT_O

Configures Start of

Block Protection

OTP

1 = BP starts at bottom (Low address).

0 = BP starts at top (High address).

RFU

Reserved for Future

Use

RFU

Reserved.

BPNV_O

Configures BP2-0 in

Status Register

OTP

1 = Volatile.

0 = Non-Volatile.

TBPARM_O

Configures

Parameter Sectors

location

OTP

1 = 4-kB physical sectors at top, (high address).

0 = 4-kB physical sectors at bottom (Low address).

RFU in uniform sector configuration.

QUAD_NV

Quad Non-Volatile

Non-Volatile

Provides the default state for the QUAD bit.

FREEZE_D

FREEZE Default

Non-Volatile

Read Only

Provides the default state for the Freeze bit. Not user

programmable.

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