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S25FS-S Datasheet(PDF) 92 Page - SPANSION

Part # S25FS-S
Description  MirrorBit Flash Non-Volatile Memory
PDF  154 Pages
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Manufacturer  SPANSION [SPANSION]
Direct Link  http://www.spansion.com
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S25FS-S Datasheet(HTML) 92 Page - SPANSION

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92
S25FS-S Family
S25FS-S_00_04 November 6, 2013
Data
Sheet
(Pre limin ar y)
Figure 10.1 Read Identification (RDID) Command Sequence
This command is also supported in QPI Mode. In QPI Mode the instruction is shifted in on IO0-IO3 and the
returning data is shifted out on IO0-IO3.
Figure 10.2 Read Identification (RDID) QPI Mode Command
10.2.2
Read Quad Identification (RDQID AFh)
The Read Quad Identification (RDQID) command provides read access to manufacturer identification, device
identification, and Common Flash Interface (CFI) information. This command is an alternate way of reading
the same information provided by the RDID command while in QPI Mode. In all other respects the command
behaves the same as the RDID command.
The command is recognized only when the device is in QPI Mode (CR2V[6]=1). The instruction is shifted in
on IO0-IO3. After the last bit of the instruction is shifted into the device, a byte of manufacturer identification,
two bytes of device identification, extended device identification, and CFI information will be shifted
sequentially out on IO0-IO3. As a whole this information is referred to as ID-CFI. See Device ID and Common
Flash Interface (ID-CFI) Address Map on page 143 for the detail description of the ID-CFI contents.
Continued shifting of output beyond the end of the defined ID-CFI address space will provide undefined data.
The command sequence is terminated by driving CS# to the logic high state anytime during data output.
The maximum clock frequency for the command is 133 MHz.
Figure 10.3 Read Quad Identification (RDQID) Command Sequence
CS#
SCK
SI
SO
Phase
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Instruction
Data1
DataN
CS#
SCLK
IO0
IO1
IO2
IO3
Phase
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
Instruction
D1
D2
D3
D4
D5
CS#
SCLK
IO0
IO1
IO2
IO3
Phase
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
7
3
7
3
Instruction
D1
D2
D3
D4
D5



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