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DM383 Datasheet(PDF) 1 Page - Texas Instruments |
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DM383 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 267 page  DM383 www.ti.com SPRS870B – APRIL 2013 – REVISED DECEMBER 2013 DM383 DaVinci™ Digital Media Processor Check for Samples: DM383 1 High-Performance System-on-Chip (SoC) 1.1 Features 123 – Hardware Face Detection for up to 35 Faces • High-Performance DaVinci Digital Media Per Frame Processors • Programmable High-Definition Video Image – Up to 1000-MHz ARM® Cortex™-A8 RISC Coprocessing (HDVICP v2) Engine Processor – Encode, Decode, Transcode Operations – Up to 2000 ARM Cortex-A8 MIPS – H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 • ARM Cortex-A8 Core SP/ASP, JPEG/MJPEG – ARMv7 Architecture • Media Controller • In-Order, Dual-Issue, Superscalar – Controls the HDVPSS, HDVICP2, and ISS Processor Core • Endianness • NEON™ Multimedia Architecture – ARM Instructions and Data – Little Endian • Supports Integer and Floating Point • HD Video Processing Subsystem (HDVPSS) • Jazelle® RCT Execution Environment – Two 165-MHz HD Video Capture Inputs • ARM Cortex-A8 Memory Architecture • One 16- or 24-Bit Input, Splittable Into – 32KB of Instruction and Data Caches Dual 8-Bit SD Capture Ports – 256KB of L2 Cache with ECC • One 8-, 16-, or 24-Bit HD Input and 8-Bit – 64KB of RAM, 48KB of Boot ROM SD Input Capture Port • 256KB of On-Chip Memory Controller (OCMC) – Two 165-MHz HD Video Display Outputs RAM • One 16-, 24-, or 30-Bit and One 16- or 24- • Imaging Subsystem (ISS) Bit Output – Camera Sensor Connection – Component HD Analog Output • Parallel Connection for Raw (up to 16-Bit) – Composite Analog Output and BT.656/BT.1120 (8- or 16-Bit) – Digital HDMI 1.3 Transmitter with Integrated • CSI2 Serial Connection PHY – Image Sensor Interface (ISIF) for Handling – Advanced Video Processing Features Such Image and Video Data From the Camera as Scan, Format, and Rate Conversion Sensor – Three Graphics Layers and Compositors – Image Pipe Interface (IPIPEIF) for Image and • 32-Bit DDR2, DDR3, and DDR3L SDRAM Video Data Connection Between Camera Interface Sensor, ISIF, IPIPE, and DRAM – Supports up to 400 MHz for DDR2, 533 MHz – Image Pipe (IPIPE) for Real-Time Image and for DDR3, and 533 MHz for DDR3L Video Processing – Up to Two x 16 Devices, 2GB of Total – Resizer Address Space • Resizing Image and Video From 1/16x to – Dynamic Memory Manager (DMM) 8x • Programmable Multi-Zone Memory • Generating Two Different Resizing Mapping Outputs Concurrently • Enables Efficient 2D Block Accesses • Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB, and AF) • Supports Tiled Objects in 0°, 90°, 180°, or Control 270° Orientation and Mirroring • Face Detect (FD) Engine 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 Device/BIOS, XDS are trademarks of Texas Instruments. 3 All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2013, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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