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APA150 Datasheet(PDF) 60 Page - Microsemi Corporation

Part # APA150
Description  ProASICPLUS Flash Family FPGAs
PDF  174 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

APA150 Datasheet(HTML) 60 Page - Microsemi Corporation

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ProASICPLUS Flash Family FPGAs
1- 56
v5.2
Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Note: The plot shows the normal operation status.
Figure 1-32 • Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)
Table 1-51 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = 0°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS
↑
2.0
ns
OCH
Old DO valid from RCLKS
↑
0.75
ns
RACH
RADDR hold from RCLKS
↑
0.5
ns
RACS
RADDR setup to RCLKS
↑
1.0
ns
RDCH
RDB hold from RCLKS
↑
0.5
ns
RDCS
RDB setup to RCLKS
↑
1.0
ns
RPCA
New RPE access from RCLKS
↑
4.0
ns
RPCH
Old RPE valid from RCLKS
↑
1.0
ns
Note: All –F speed grade devices are 20% slower than the standard numbers.
RCLKS
RPE
DO
New Valid Data Out
Cycle Start
New RPE Out
RADDR
New Valid
Address
RDB, RBLKB
tRACS
tOCA
tRPCH
tOCH
tRPCA
tCML
tCMH
tCCYC
tRACH
tRDCH
tRDCS
Old Data Out
Old RPE Out



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