APA150 datasheet(16/174 Pages) MICROSEMI

16 / 174 page

ProASICPLUS Flash Family FPGAs

1- 12

v5.2

The TAP controller receives two control inputs (TMS and

TCK) and generates control and clock signals for the rest

of the test logic architecture. On power-up, the TAP

controller enters the Test-Logic-Reset state. To guarantee

a reset of the controller from any of the possible states,

TMS must remain high for five TCK cycles. The TRST pin

may also be used to asynchronously place the TAP

controller in the Test-Logic-Reset state.

ProASICPLUS devices support three types of test data

registers: bypass, device identification, and boundary

scan. The bypass register is selected when no other

test data transfer to other devices in a test data path.

The 32-bit device identification register is a shift register

with four fields (lowest significant byte (LSB), ID number,

part number and version). The boundary-scan register

observes and controls the state of each I/O pin.

Each I/O cell has three boundary-scan register cells, each

with a serial-in, serial-out, parallel-in, and parallel-out

pin. The serial pins are used to serially connect all the

boundary-scan register cells in a device into a boundary-

scan register chain, which starts at the TDI pin and ends

at the TDO pin. The parallel ports are connected to the

internal core logic tile and the input, output, and control

ports of an I/O buffer to capture and load data into the

Figure 1-13 • TAP Controller State Diagram

Test-Logic

Reset

Run-Test/

Idle

Select-DR-

Scan

Capture-DR

Shift-DR

Exit-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR-

Scan

Capture-IR

Shift-IR

Exit-IR

Pause-IR

Exit2-IR

Update-IR

APA150 Datasheet(PDF) 16 Page - Microsemi Corporation

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