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APA150 Datasheet(PDF) 64 Page - Microsemi Corporation

Part # APA150
Description  ProASICPLUS Flash Family FPGAs
PDF  174 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

APA150 Datasheet(HTML) 64 Page - Microsemi Corporation

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ProASICPLUS Flash Family FPGAs
1- 60
v5.2
Synchronous SRAM Write
Note: The plot shows the normal operation status.
Figure 1-36 • Synchronous SRAM Write
Table 1-55 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
DCH
DI hold from WCLKS
↑
0.5
ns
DCS
DI setup to WCLKS
↑
1.0
ns
WACH
WADDR hold from WCLKS
↑
0.5
ns
WDCS
WADDR setup to WCLKS
↑
1.0
ns
WPCA
New WPE access from WCLKS
↑
3.0
ns
WPE is invalid while
PARGEN is active
WPCH
Old WPE valid from WCLKS
↑
0.5
ns
WRCH, WBCH WRB & WBLKB hold from WCLKS
↑
0.5
ns
WRCS, WBCS
WRB & WBLKB setup to WCLKS
↑
1.0
ns
Notes:
1. On simultaneous read and write accesses to the same location, DI is output to DO.
2. All –F speed grade devices are 20% slower than the standard numbers.
WCLKS
WPE
WADDR, DI
WRB, WBLKB
Cycle Start
tWRCH, tWBCH
tWRCS, tWBCS
tDCS, tWDCS
tWPCH
tDCH, tWACH
tWPCA
tCMH
tCML
tCCYC



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