AM79C975VCW datasheet(186/304 Pages) AMD

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186

Am79C973/Am79C975

P R E L I M INARY

Read/Write accessible always.

APEP

set

during

H_RESET and is unaffected by

S_RESET and the STOP bit.

10-8

APDW

Auto-Poll Dwell Time. APDW de-

termines the dwell time between

PHY

Management

Frame

accesses

when

Auto-Poll

turned on. See Table 38.

Read/Write accessible always.

APDW is set to

100h after

H_RESET and is unaffected by

S_RESET and the STOP bit.

DANAS

Disable

Auto-Negotiation

Auto

Setup. When DANAS is set, the

Am79C973/Am79C975 controller

after a H_RESET or S_RESET

will remain dormant and not auto-

matically startup the Auto-Negoti-

ation section or the enhanced

automatic port selection section.

Instead,

the

Am79C973/

Am79C975 controller will wait for

the software driver to setup the

Auto-Negotiation portions of the

device. The PHY Address and

Data programming in BCR33 and

BCR34

still

valid.

The

Am79C973/Am79C975 controller

will not generate any manage-

ment frames unless Auto-Poll is

enabled.

Read/write

accessible

always.

DANAS is set to 0 by H_RESET

and is unaffected by S_RESET

and the STOP bit.

XPHYRST

PHY Reset. When XPHYRST is

set, the Am79C973/Am79C975

controller after an H_RESET or

S_RESET will issue manage-

ment frames that will reset the

PHY. This bit is needed when

there is no way to guarantee the

state of the external PHY. This bit

must be reprogrammed after ev-

ery H_RESET.

Read/Write accessible always.

XPHYRST

set

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYRST is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYANE

PHY Auto-Negotiation Enable.

This bit will force the PHY into en-

abling Auto-Negotiation. When

set

the

Am79C973/

Am79C975 controller will send a

management

frame

disabling

Auto-Negotiation.

Read/Write accessible always.

XPHYANE

set

H_RESET and is unaffected by

S_RESET and the STOP bit.

XPHYANE is only valid when the

internal Network Port Manager is

scanning for a network port.

XPHYFD

PHY Full Duplex. When set, this

bit will force the PHY into full du-

plex when Auto-Negotiation is not

enabled.

Read/Write accessible always.

XPHYFD

set

H_RESET, and is unaffected by

S_RESET and the STOP bit.

XPHYSP

PHY Speed. When set, this bit

will force the PHY into 100 Mbps

mode when Auto-Negotiation is

not enabled.

Read/Write accessible always.

XPHYSP

set

H_RESET, and is unaffected by

S_RESET and the STOP bit.

RES

Reserved location. Written as ze-

ros and read as undefined.

MIIILP

Media Independent Interface In-

ternal Loopback. When set, this

bit will cause the internal portion

of the MII data port to loopback

on itself. The interface is mapped

the

following

way.

The

Table 38. APDW Values

APDW

Auto-Poll

 Dwell Time

000

Continuous (26

µs @ 2.5 MHz)

001

Every 128 MDC cycles (103

µs @ 2.5 MHz)

010

Every 256 MDC cycles (206

µs @ 2.5 MHz)

011

Every 512 MDC cycles (410

µs @ 2.5 MHz)

100

Every 1024 MDC cycles (819

µs @ 2.5 MHz)

101

Every 2048 MDC cycles (1640

µs @ 2.5 MHz)

110-111 Reserved

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