AM79C975VCW datasheet(182/304 Pages) AMD

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182

Am79C973/Am79C975

P R E L I M INARY

LOLATRX

Low Latency Receive. When the

LOLATRX bit is set to 1, the

Am79C973/Am79C975 controller

will switch to an architecture ap-

plicable to cut-through switches.

The Am79C973/Am79C975 con-

troller will assert a receive frame

DMA after only 16 bytes of the

current receive frame has been

received regardless of where the

RCVFW (CSR80, bits 13-12) are

set. The watermark is a fixed val-

ue and cannot be changed. The

receive

FIFOs

will

NO_SRAM mode while all trans-

mit traffic is buffered through the

SRAM. This bit is only valid and

the low latency receive only en-

abled

when

the

SRAM_SIZE

(BCR25, bits 7-0) bits are non-ze-

ro. SRAM_BND (BCR26, bits 7-

0) has no meaning when the

Am79C973/Am79C975 controller

is in the Low Latency mode. See

the section on SRAM Configura-

tion for more details.

When the LOLATRX bit is set to

the

Am79C973/Am79C975

controller will return to a normal

receive configuration. The runt

packet accept bit (RPA, CSR124,

bit 3) must be set when LOLA-

TRX is set.

CAUTION: To provide data in-

tegrity when switching into

and out of the low latency

mode,

NOT

SET

the

FASTSPNDE (CSR7, bit 15) bit

when setting the SPND bit. Re-

ceive frames WILL be overwrit-

ten

and

the

Am79C973/

Am79C975 controller may give

erratic behavior when it is en-

able again. The minimum al-

lowed number of pages is four.

The

Am79C973/Am79C975

controller will not operate cor-

rectly in the LOLATRX mode

with less than four pages of

memory.

Read/Write accessible only when

the STOP bit is set. LOLATRX is

cleared to 0 after H_RESET or

S_RESET and is unaffected by

STOP.

13-6

RES

Reserved locations. Written as

zeros and read as undefined.

5-3

EBCS

Expansion Bus Clock Source.

These bits are used to select the

source of the fundamental clock

to drive the SRAM and Expansion

ROM access cycles. Table 35

shows the selected clock source

for the various values of EBCS.

Note that the actual frequency

that the Expansion Bus access

cycles run at is a function of both

the

EBCS

and

CLK_FAC

(BCR27, bits 2-0) bit field set-

tings. When EBCS is set to either

the PCI clock or the Time Base

clock, no external clock source is

required as the clocks are routed

internally and the EBCLK pin

should be pulled to VDD through

a resistor.

Read accessible always; write

accessible only when the STOP

bit is set. EBCS is set to 000b

(PCI

clock

selected)

during

H_RESET and is unaffected by

S_RESET or the STOP bit.

Note: The clock frequency driv-

ing the Expansion Bus access cy-

cles that results from the settings

of the EBCS and CLK FAC bits

must not exceed 33 MHz at any

time. When EBCS is set to either

the PCI clock or the Time Base

clock, no external clock source is

required because the clocks are

routed internally and the EBCLK

pin should be pulled to VDD

through a resistor.

CAUTION: Care should be ex-

ercised when choosing the PCI

clock pin because of the nature

of the PCI clock signal. The PCI

specification states that the

PCI clock can be stopped. If

Table 35. EBCS Values

EBCS

Expansion Bus Clock Source

000

CLK pin (PCI Clock)

001

Time Base Clock

010

EBCLK pin

011

Reserved

1XX

Reserved

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