AM79C975VCW datasheet(181/304 Pages) AMD

181 / 304 page

Am79C973/Am79C975

181

P R E L I M INARY

31-8

RES

Reserved locations. Written as

zeros and read as undefined.

7-0

SRAM_SIZE SRAM Size. Specifies the upper

8 bits of the 16-bit total size of the

SRAM

buffer.

Each

bit

SRAM_SIZE accounts for a 512-

byte page. The starting address

for the lower 8 bits is assumed to

be 00h and the ending address

for the lower is assumed to be

FFh. Therefore, the maximum ad-

dress range is the starting ad-

dress of 0000h to ending address

((SRAM_SIZE

+1)

256

words)

17FFh.

SRAM_SIZE value of all zeros

specifies that no SRAM will be

used and the internal FIFOs will

be joined into a contiguous FIFO

similar to the PCnet-PCI II con-

troller.

Note:

The

minimum

allowed

number of pages is eight for nor-

mal

network

operation.

The

Am79C973/Am79C975 controller

will not operate correctly with less

than the eight pages of memory.

When the minimum number of

pages is used, these pages must

be allocated four each for trans-

mit and receive.

CAUTION:

Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM_SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_SIZE is set to

000000b during H_RESET and is

unaffected

S_RESET

STOP.

BCR26: SRAM Boundary Register

Bit

Name

Description

Note: Bits 7-0 in this register are programmable

through the EEPROM.

31-8

RES

Reserved locations. Written as

zeros and read as undefined.

7-0

SRAM_BND

SRAM Boundary. Specifies the

upper 8 bits of the 16-bit address

boundary where the receive buffer

begins in the SRAM. The transmit

buffer in the SRAM begins at ad-

dress 0 and ends at the address

located just before the address

specified by SRAM_BND. There-

fore, the receive buffer always be-

gins on a 512 byte boundary. The

lower bits are assumed to be ze-

ros. SRAM_BND has no effect in

the Low Latency Receive mode.

Note:

The

minimum

allowed

number of pages is four. The

Am79C973/Am79C975 controller

will not operate correctly with less

than four pages of memory per

queue.

See

Table

for

SRAM_BND programming de-

tails.

CAUTION:

Programming

SRAM_BND and SRAM_SIZE

to the same value will cause

data corruption except in the

case where SRAM SIZE is 0.

Read accessible always; write

accessible only when the STOP

bit is set. SRAM_BND is set to

00000000b

during

H_RESET

and is unaffected by S_RESET or

STOP.

BCR27: SRAM Interface Control Register

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

PTR TST

Reserved. Reserved for manu-

facturing tests. Written as zero

and read as undefined.

Note: Use of this bit will cause

data corruption and erroneous

operation.

Read/Write accessible always.

PTR_TST

set

H_RESET and is unaffected by

S_RESET and the STOP bit.

Table 34. SRAM_BND Programming

SRAM Addresses

SRAM_BND [7:0]

Minimum SRAM_BND

Address

04h

Maximum SRAM_BND Address

13h

AM79C975VCW Datasheet(PDF) 181 Page - Advanced Micro Devices

AM79C975VCW Datasheet(HTML) 181 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL