AM79C975VCW datasheet(178/304 Pages) AMD

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178

Am79C973/Am79C975

P R E L I M INARY

while EEN = 1, then setup and

hold times of the EEDI pin value

with respect to the EESK signal

edge are not guaranteed.

ESK has no effect on the EESK

pin unless the PREAD bit is set to

0 and the EEN bit is set to 1.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set. ESK

is reset to 1 by H_RESET and is

not affected by S_RESET or

STOP.

EDI/EDO

EEPROM

Data

In/EEPROM

Data Out. Data that is written to

this bit will appear on the EEDI

output of the interface, except

when the PREAD bit is set to 1 or

the EEN bit is set to 0. Data that

is read from this bit reflects the

value of the EEDO input of the in-

terface.

EDI/EDO has no effect on the

EEDI pin unless the PREAD bit is

set to 0 and the EEN bit is set to

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set. EDI/

EDO is reset to 0 by H_RESET

and is not affected by S_RESET

or STOP.

BCR20: Software Style

This register is an alias of the location CSR58. Accesses

to and from this register are equivalent to accesses to

CSR58.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-11 RES

Reserved locations. Written as

zeros and read as undefined.

APERREN

Advanced Parity Error Handling

Enable. When APERREN is set

to 1, the BPE bits (RMD1 and

TMD1, bit 23) start having a

meaning. BPE will be set in the

descriptor associated with the

buffer that was accessed when a

data parity error occurred. Note

that since the advanced parity er-

ror handling uses an additional bit

in the descriptor, SWSTYLE (bits

7-0 of this register) must be set to

2 or 3 to program the Am79C973/

Am79C975 controller to use 32-

bit software structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur when

the Am79C973/Am79C975 con-

troller is the target of the transfer.

Read anytime; write accessible

only when either the STOP or the

SPND bit is set. APERREN is

cleared by H_RESET and is not

affected by S_RESET or STOP.

RES

Reserved locations. Written as

zeros; read as undefined.

SSIZE32

Software Size 32 bits. When set,

this

bit

indicates

that

the

Am79C973/Am79C975 controller

utilizes 32-bit software structures

for the initialization block and the

transmit and receive descriptor

entries. When cleared, this bit in-

dicates

that

the

Am79C973/

Am79C975 controller utilizes 16-

bit software structures for the ini-

tialization block and the transmit

and receive descriptor entries. In

this

mode,

the

Am79C973/

Am79C975 controller is back-

wards

compatible

with

the

Am7990 LANCE and Am79C960

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined

the

Am79C973/

Am79C975 controller according

to the setting of the Software

Style (SWSTYLE, bits 7-0 of this

Read

accessible

always.

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

AM79C975VCW Datasheet(PDF) 178 Page - Advanced Micro Devices

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