AM79C975VCW datasheet(175/304 Pages) AMD

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Am79C973/Am79C975

175

P R E L I M INARY

and is not affected by S_RESET

or STOP.

4-3

PHYSEL[1:0]

PHYSEL[1:0] bits allow for soft-

ware controlled selection of differ-

ent operation and test modes.

The normal mode of operation is

when both bits 0 and 1 are set to

0 to select the Expansion ROM/

Flash. Setting bit 0 to 1 and bit 1

to 0 allows snooping of the inter-

nal MII-compatible bus to allow

External Address Detection Inter-

face

(EADI).

Setting

PHY-

SEL[1:0]

enables

the

external MII mode. Since the in-

ternal 10/100 PHY is disabled in

this

mode,

the

Am79C973/

Am79C975 controller behaves

like an Am79C972 PCnet-FAST+

device. Tehese controllers are

not designed to support two

PHYs at a time as only one PHY

can be used at a given time. An

external or internal PHY can be

used by reconfiguring the EE-

PROM or the BCI18 register. See

the following table for details.

Read accessible always, these

bits can only be written from the

EEPROM unless a write-enable

bit BCR2[13], is set. PHYSEL

[1:0] is cleared by H_RESET and

is not affected by S_RESET or

STOP.

2-0

LINBC

Reserved locations. Read acces-

sible always; write accessible

only when either the STOP or the

SPND bit is set. After H_RESET,

the value in these bits will be

001b. The setting of these bits

have

effect

any

Am79C973/Am79C975 controller

function. LINBC is not affected by

S_RESET or STOP.

BCR19: EEPROM Control and Status

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

PVALID

EEPROM Valid status bit. Read

accessible only. PVALID is read

only; write operations have no ef-

fect. A value of 1 in this bit indi-

cates that a PREAD operation

has occurred, and that (1) there is

an EEPROM connected to the

Am79C973/Am79C975 controller

interface pins and (2) the con-

tents read from the EEPROM

have passed the checksum verifi-

cation operation.

A value of 0 in this bit indicates a

failure in reading the EEPROM.

The checksum for the entire 82

bytes of EEPROM is incorrect or

no EEPROM is connected to the

interface pins.

PVALID

set

during

H_RESET and is unaffected by

S_RESET or the STOP bit. How-

ever, following the H_RESET op-

eration, an automatic read of the

EEPROM will be performed. Just

as is true for the normal PREAD

command, at the end of this auto-

matic read operation, the PVALID

bit may be set to 1. Therefore,

H_RESET will set the PVALID bit

to 0 at first, but the automatic EE-

PROM read operation may later

set PVALID to a 1.

If PVALID becomes 0 following

an EEPROM read operation (ei-

ther automatically generated af-

ter

H_RESET,

requested

through PREAD), then all EE-

PROM-programmable BCR loca-

tions

will

reset

their

H_RESET values. The content of

the Address PROM locations,

however, will not be cleared.

If no EEPROM is present at the

EESK, EEDI, and EEDO pins,

then all attempted PREAD com-

mands will terminate early and

PVALID will not be set. This ap-

plies to the automatic read of the

PHYSEL [1:0]

Mode

Expansion ROM/Flash - Normal Mode

EADI/Internal MII Snoop Mode

Full MII Mode - An External PHY

Required

Reserved

AM79C975VCW Datasheet(PDF) 175 Page - Advanced Micro Devices

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