AM79C975VCW datasheet(171/304 Pages) AMD

171 / 304 page

Am79C973/Am79C975

171

P R E L I M INARY

LNKSE

Link Status Enable. When this bit

is set, a value of 1 will be passed

to the LEDOUT bit in this register

in Link Pass state.

Read/Write accessible always.

LNKSE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

RCVME

Receive Match Status Enable.

When this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network that has

passed the address match func-

tion for this node. All address

matching modes are included:

physical, logical filtering, broad-

cast, and promiscuous.

Read/Write accessible always.

RCVME is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

XMTE

Transmit Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible always.

XMTE is set to 1 by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

RES

Reserved location. Written and

read as zeros.

RCVE

Receive Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

tivity on the network.

Read/Write accessible always.

RCVE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

RES

Reserved location. Written and

read as zeros.

COLE

Collision Status Enable. When

this bit is set, a value of 1 is

passed to the LEDOUT bit in this

activity on the network.

Read/Write accessible always.

COLE is cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

BCR9: Full-Duplex Control

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-3

RES

Reserved locations. Written as

zeros and read as undefined.

FDRPAD

Full-Duplex Runt Packet Accept

Disable. When FDRPAD is set to

1 and full-duplex mode is en-

abled,

the

Am79C973/

Am79C975 controller will only re-

ceive frames that meet the mini-

mum Ethernet frame length of 64

bytes. Receive DMA will not start

until at least 64 bytes or a com-

plete frame have been received.

By default, FDRPAD is cleared to

The

Am79C973/Am79C975

controller will accept any length

frame and receive DMA will start

according to the programming of

the

receive

FIFO

watermark.

Note that there should not be any

runt packets in a full-duplex net-

work, since the main cause for

runt packets is a network collision

and there are no collisions in a

full-duplex

network.

This

bit

needs to be set if in full-duplex

mode and external address rejec-

tion (EAR (BCR9, bit 2)) function-

ality is desired.

Read/Write accessible always.

FDRPAD is cleared by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

RES

Reserved locations. Written as

zeros and read as undefined.

FDEN

Full-Duplex Enable. FDEN con-

trols whether full-duplex opera-

tion is enabled. When FDEN is

cleared and the Auto-Negotiation

is disabled, full-duplex operation

not

enabled

and

the

Am79C973/Am79C975 controller

AM79C975VCW Datasheet(PDF) 171 Page - Advanced Micro Devices

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