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AM79C975VCW Datasheet(PDF) 167 Page - Advanced Micro Devices

Part # AM79C975VCW
Description  PCnet??FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller with Integrated PHY
PDF  304 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM79C975VCW Datasheet(HTML) 167 Page - Advanced Micro Devices

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Am79C973/Am79C975
167
P R E L I M INARY
11-10 RES
Reserved locations. Written and
read as zeros.
9
MPSE
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when Magic Packet
mode is enabled and a Magic
Packet frame is detected on the
network.
Read/Write accessible always.
MPSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
8
FDLSE
Full-Duplex Link Status Enable.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LED-
OUT signal when the Am79C973/
Am79C975 controller is function-
ing in a Link Pass state and full-
duplex
operation
is
enabled.
When
the
Am79C973/
Am79C975 controller is not func-
tioning in a Link Pass state with
full-duplex operation being en-
abled, a value of 0 is passed to
the LEDOUT signal.
Read/Write accessible always.
FDLSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
7
PSE
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new oc-
currence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
Read/Write accessible always.
PSE is set to 1 by H_RESET and
is not affected by S_RESET or
setting the STOP bit.
6
LNKSE
Link Status Enable. When this bit
is set, a value of 1 will be passed
to the LEDOUT bit in this register
in Link Pass state.
Read/Write accessible always.
LNKSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
5
RCVME
Receive Match Status Enable.
When this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network that has
passed the address match func-
tion for this node. All address
matching modes are included:
physical, logical filtering, broad-
cast, and promiscuous.
Read/Write accessible always.
RCVME is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
4
XMTE
Transmit Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is transmit
activity on the network.
Read/Write accessible always.
XMTE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
3
RES
Reserved location. Written and
read as zeros.
2
RCVE
Receive Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is receive ac-
tivity on the network.
Read/Write accessible always.
RCVE is set to 1 by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
1
RES
Reserved location. Written and
read as zeros.
0
COLE
Collision Status Enable. When
this bit is set, a value of 1 is
passed to the LEDOUT bit in this
register when there is collision
activity on the network.
Read/Write accessible always.
COLE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.



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