AM79C975VCW datasheet(163/304 Pages) AMD

163 / 304 page

Am79C973/Am79C975

163

P R E L I M INARY

value in the D5 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M2 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

APROMWE Address PROM Write Enable.

The Am79C973/Am79C975 con-

troller contains a shadow RAM on

board for storage of the first 16

bytes loaded from the serial EE-

PROM.

Accesses to Address

PROM I/O Resources will be di-

rected toward this RAM. When

APROMWE is set to 1, then write

access to the shadow RAM will

be enabled.

Read/Write accessible always.

APROMWE is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

INTLEVEL

Interrupt Level. This bit allows the

interrupt output signals to be pro-

grammed

for

level

edge-

sensitive applications.

When INTLEVEL is cleared to 0,

the INTA pin is configured for

level-sensitive

applications.

this mode, an interrupt request is

signaled by a low level driven on

the INTA pin by the Am79C973/

Am79C975 controller. When the

interrupt is cleared, the INTA pin

is tri-stated by the Am79C973/

Am79C975 controller and al-

lowed to be pulled to a high level

by an external pullup device. This

mode is intended for systems

which allow the interrupt signal to

be shared by multiple devices.

When INTLEVEL is set to 1, the

INTA pin is configured for edge-

sensitive

applications.

this

mode, an interrupt request is sig-

naled by a high level driven on

the INTA pin by the Am79C973/

Am79C975 controller. When the

interrupt is cleared, the INTA pin

is driven to a low level by the

Am79C973/Am79C975

control-

ler. This mode is intended for sys-

tems that do not allow

interrupt

channels to be shared by multiple

devices.

INTLEVEL should not be set to 1

when the Am79C973/Am79C975

controller is used in a PCI bus ap-

plication.

Read/Write accessible always.

INTLEVEL is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

I2C_M1

(Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D4 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M1 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

I2C_M0

(Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D3 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M0 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

I2C_N2

(Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D2 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_N2 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

EADISEL

EADI Select. When set to 1, this

bit enables the three EADI inter-

face pins that are multiplexed

with other functions. EESK/LED1

becomes

SFBD,

EEDO/LED3

becomes

MIIRXFRTGD,

and

LED2 becomes MIIRXFRTGE.

AM79C975VCW Datasheet(PDF) 163 Page - Advanced Micro Devices

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