AM79C975VCW datasheet(162/304 Pages) AMD

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162

Am79C973/Am79C975

P R E L I M INARY

BCR2: Miscellaneous Configuration

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

SMIUEN

(For Am79C975 only) SMIUEN is

used to enable/disable the Serial

Management Interface Unit in the

Am79C975 controller.

If SMIUEN is set to 0 (default),

the SMIU is disable. If SMIUEN is

set to 1, the SMIU is enabled.

Read/Write accessible always.

SMIUEN is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

DISSCR_SFEX

This bit is used to disable the

scrambler/descrambler when the

device is used in PECL mode.

This bit defaults to 0, which en-

ables the scrambler/descrambler

for MLT3 applications.

When DISSCR_SFEX is set to 1,

the scrambler will be disabled for

fiber applications.

Read/Write accessible always.

This bit is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

PHYSELEN This

bit

enables

writes

BCR18[4:3] for software selec-

tion of various operation and test

modes. When PHYSELEN is set

to 0 (default), the two bits can

only be written from the EE-

PROM. When PHYSELEN is set

to 1, writes to BCR18[4:3] are en-

abled.

Read/Write accessible always.

PHYSELEN is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

LEDPE

LED

Program

Enable.

When

LEDPE is set to 1, programming

the

LED0

(BCR4),

LED1

(BCR5),

LED2

(BCR6),

and

LED3 (BCR7) registers is en-

abled. When LEDPE is cleared to

0, programming of LED0 (BCR4),

LED1 (BCR5), LED2 (BCR6),

and LED3 (BCR7) registers is

disabled. Writes to those regis-

ters will be ignored.

Read/Write accessible always.

LEDPE

cleared

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

RESET_SFEX

This bit is used to reset the inter-

nal PHY. When RESET_SFEX is

set to 1, the internal PHY will stay

reset

until

RESET_SFEX

cleared to 0.

Read/Write accessible always.

RESET_SFEX is cleared to 0 by

H_RESET and is unaffected by

S_RESET or by setting the STOP

bit.

I2C_M3

(Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

value in the D6 bit position (see

Appendix B on SMIU Bus Fre-

quency.

Read/Write accessible always.

I2C_M3 is cleared by H_RESET

and is unaffected by S_RESET or

by setting the STOP bit.

I2C_M2

(Am79C975 only). This bit is used

to set the operating frequency of

the SMIU core. It represents the

M_IP_ADR[15:0]

0000h

Management IP Address [15:0]

Yes

M_IPADR[31:16]

0000h

Management IP Address [31:16]

Yes

Table 30. BCR Registers (Am79C975)

AM79C975VCW Datasheet(PDF) 162 Page - Advanced Micro Devices

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