AM79C975VCW datasheet(172/304 Pages) AMD

172 / 304 page

172

Am79C973/Am79C975

P R E L I M INARY

will always operate in the half-du-

plex mode. When FDEN is set,

the Am79C973/Am79C975 con-

troller will operate in full-duplex

mode. Do not set this bit when

Auto-Negotiation is enabled.

Read/Write accessible always.

FDEN is reset to 0 by H_RESET,

and is unaffected by S_RESET

and the STOP bit.

BCR16: I/O Base Address Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-5

IOBASEL

Reserved

locations.

After

H_RESET, the value of these bits

will be undefined. The settings of

these bits will have no effect on

any Am79C973/Am79C975 con-

troller function. It is only included

for software compatibility with

other PCnet family devices.

Read/Write accessible always.

IOBASEL is not affected by

S_RESET or STOP.

4-0

RES

Reserved locations. Written as

zeros, read as undefined.

BCR17: I/O Base Address Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

IOBASEU

Reserved

locations.

After

H_RESET, the value in this regis-

ter will be undefined. The settings

of this register will have no effect

on any Am79C973/Am79C975

controller function. It is only in-

cluded for software compatibility

with other PCnet family devices.

Read/Write accessible always.

IOBASEU is not affected by

S_RESET or STOP.

BCR18: Burst and Bus Control Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 ROMTMG

Expansion ROM Timing. The val-

ue of ROMTMG is used to tune

the

timing

for

all

EBDATA

(BCR30)

accesses

Flash/

EPROM as well as all Expansion

ROM accesses to Flash/EPROM.

ROMTMG, during read opera-

tions, defines the time from when

the Am79C973/Am79C975 con-

troller drives the lower 8 or 16 bits

of the Expansion Bus Address

bus to when the Am79C973/

Am79C975 controller latches in

the data on the 8 or 16 bits of the

Expansion

Bus

Data

inputs.

ROMTMG, during write opera-

tions, defines the time from when

the Am79C973/Am79C975 con-

troller drives the lower 8 or 16 bits

of the Expansion Bus Data to

when the EBWE and EROMCS

deassert.

The register value specifies the

time in number of clock cycles +1

according to Table 31.

Note: Programming ROMTNG

with a value of 0 is not permitted.

The access time for the Expan-

sion

ROM

the

EBDATA

(BCR30) device (tACC) during

read operations can be calculat-

ed by subtracting the clock to out-

put delay for the EBUA_EBA[7:0]

outputs (tv_A_D) and by subtract-

ing the input to clock setup time

for the EBD[7:0] inputs (ts_D)

from the time defined by ROMT-

MG:

tACC = ROMTMG * CLK period

*CLK_FAC - (tv_A_D) - (ts_D)

Table 31. ROMTNG Programming Values

ROMTMG (bits 15-12)

No. of Expansion Bus Cycles

1h<=n <=Fh

n+1

AM79C975VCW Datasheet(PDF) 172 Page - Advanced Micro Devices

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