AM79C975VCW datasheet(176/304 Pages) AMD

176 / 304 page

176

Am79C973/Am79C975

P R E L I M INARY

EEPROM after H_RESET, as

well as to host-initiated PREAD

commands.

PREAD

EEPROM Read command bit.

When this bit is set to a 1 by the

host, the PVALID bit (BCR19, bit

15) will immediately be reset to a

0, and then the Am79C973/

Am79C975 controller will perform

a read operation of 82 bytes from

the EEPROM through the inter-

face. The EEPROM data that is

fetched during the read will be

stored in the appropriate internal

registers

board

the

Am79C973/Am79C975

control-

ler. Upon completion of the EE-

PROM

read

operation,

the

Am79C973/Am79C975 controller

will assert the PVALID bit. EE-

PROM contents will be indirectly

accessible to the host through

read accesses to the Address

PROM (offsets 0h through Fh)

and through read accesses to

other EEPROM programmable

registers. Note that read access-

es from these locations will not

actually access the EEPROM it-

self, but instead will access the

Am79C973/Am79C975

control-

lers internal copy of the EEPROM

contents. Write accesses to these

locations

may

change

the

Am79C973/Am79C975 controller

PROM locations will not be affect-

ed. EEPROM locations may be

accessed

directly

through

BCR19.

At the end of the read operation,

the PREAD bit will automatically

be reset to a 0 by the Am79C973/

Am79C975

controller

and

PVALID will be set, provided that

an EEPROM existed on the inter-

face pins and that the checksum

for the entire 82 bytes of EE-

PROM was correct.

Note that when PREAD is set to a

then

the

Am79C973/

Am79C975

controller

will

longer respond to any accesses

directed

toward

it,

until

the

PREAD operation has completed

successfully.

The

Am79C973/

Am79C975 controller will termi-

nate these accesses with the as-

sertion of DEVSEL and STOP

while TRDY is not asserted, sig-

naling to the initiator to discon-

nect and retry the access at a

later time.

If a PREAD command is given to

the Am79C973/Am79C975 con-

troller but no EEPROM is at-

tached to the interface pins, the

PREAD bit will be cleared to a 0,

and the PVALID bit will remain re-

set with a value of 0. This applies

to the automatic read of the EE-

PROM after H_RESET as well as

to host initiated PREAD com-

mands. EEPROM programmable

locations

board

the

Am79C973/Am79C975 controller

will be set to their default values

by such an aborted PREAD oper-

ation. For example, if the aborted

PREAD operation immediately

followed the H_RESET opera-

tion, then the final state of the EE-

PROM programmable locations

will be equal to the H_RESET

programming for those locations.

If a PREAD command is given to

the Am79C973/Am79C975 con-

troller and the auto-detection pin

(EESK/LED1/SFBD)

indicates

that no EEPROM is present, then

the EEPROM read operation will

still be attempted.

Note that at the end of the

H_RESET operation, a read of

the EEPROM will be performed

automatically. This H_RESET-

generated EEPROM read func-

tion will not proceed if the auto-

detection pin (EESK/LED1/SF-

BD) indicates that no EEPROM is

present.

Read accessible always; write

accessible only when either the

STOP or the SPND bit is set.

PREAD

set

during

H_RESET and is unaffected by

S_RESET or the STOP bit.

EEDET

EEPROM Detect. This bit indi-

cates the sampled value of the

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