AM79C975VCW datasheet(194/304 Pages) AMD

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194

Am79C973/Am79C975

P R E L I M INARY

Table 40. ANR0: PHY Control Register (Register 0)

Notes:

1. R/W = Read/Write, SC = Self Clearing, RO = Read only.

2. Soft Reset does not reset the PDX block. Refer to the Soft Reset Section for details.

3. Bits 8 and 13 have no effect if Auto-Negotiation is enabled (Bit 12 = 1).

Reg

Bits

Name

Description

Read/Write

(Note 1)

Default

Value

Soft

Reset

Soft Reset (Note 2)

When write: 1 = PHY software reset,

0 = normal operation.

When read: 1 = reset in process,

0 = reset done.

R/W, SC

014

Loopback

1 =asserts the internal LPBCK,

0 = deasserts the internal LPBCK

R/W

013

Speed Selection

(Note 3)

1 = 100 Mbps,

0 = 10 Mbps

R/W

012

Auto-Negotiation

Enable

1 = enable Auto-Negotiation,

0 = disable Auto-Negotiation

R/W

Power Down

1 = power down, 0 = normal operation

R/W

010

Isolate

1 = electrically isolate PHY

0 = normal operation

R/W

Restart Auto-

Negotiation

1 = restart Auto-Negotiation,

0 = normal operation

R/W, SC

Duplex Mode

(Note 3)

1 = full duplex,

0 = half duplex

R/W

Retains

value

Collision Test

1 = enable COL signal test,

0 = disable COL signal test

R/W

6-0

Reserved

Write as 0, ignore on read

AM79C975VCW Datasheet(PDF) 194 Page - Advanced Micro Devices

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