AM79C975VCW datasheet(192/304 Pages) AMD

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192

Am79C973/Am79C975

P R E L I M INARY

dress of the PMR word to be accessed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written until the write to BCR47 is complete. The write

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-8

PMR_B2

Pattern Match RAM Byte 2. This

byte is written into or read from

Byte 2 of the Pattern Match RAM.

Read and write accessible al-

ways. PMR_B2 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

7-0

PMR_B1

Pattern Match RAM Byte 1. This

byte is written into or read from

Byte 1 of Pattern Match RAM.

Read and write accessible al-

ways. PMR_B1 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR47: OnNow Pattern Matching Register 3

Note: This register is used to control and indirectly ac-

cess the Pattern Match RAM (PMR). When BCR45 is

written and the PMAT_MODE bit (bit 7) is 1, Pattern

Match logic is enabled. No bus accesses into PMR are

possible, and BCR46, BCR47, and all other bits in

BCR45 are ignored. When PMAT_MODE is set, a read

of BCR45, BCR46, or BCR47 returns all undefined bits

except for PMAT_MODE.

When BCR45 is written and the PMAT_MODE bit is 0,

the Pattern Match logic is disabled and accesses to the

PMR are possible. Bits 6-0 of BCR45 specify the ad-

dress of the PMR word to be accessed. Following the

write to BCR45, the PMR word may be read by reading

BCR45, BCR46 and BCR47 in any order. To write to

PMR word, the write to BCR45 must be followed by a

write to BCR46 and a write to BCR47 in that order to

complete the operation. The RAM will not actually be

written until the write to BCR47 is complete. The write

to BCR47 causes all 5 bytes (four bytes of BCR46-47

and the upper byte of the BCR45) to be written to what-

ever PMR word is addressed by bits 6:0 of BCR45.

When PMAT_MODE is 0, the contents of the word ad-

dressed by bits 6:0 of BCR45 can be read by reading

BCR45-47 in any order.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-8

PMR_B4

Pattern Match RAM Byte 4. This

byte is written into or read from

Byte 4 of Pattern Match RAM.

Read and write accessible al-

ways. PMR_B4 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

7-0

PMR_B3

Pattern Match RAM Byte 3. This

byte is written into or read from

Byte 3 of Pattern Match RAM.

Read and write accessible al-

ways. PMR_B3 is undefined after

H_RESET, and is unaffected by

S_RESET and the STOP bit.

BCR48-BCR55: Reserved Locations for Am79C975

These registers must be 00h for the Am79C973 con-

troller.

PHY Management Registers (ANRs)

The Am79C973/Am79C975 device supports the MII

basic register set and extended register set. Both sets

of registers are accessible through the PHY Manage-

ment Interface. As specified in the IEEE standard, the

basic register set consists of the Control Register (Reg-

ister 0) and the Status Register (Register 1). The ex-

tended register set consists of Registers 2 to 31

(decimal).

Table 39 lists all the registers implemented in the de-

vice. All the reserved registers should not be written to,

and reading them will return a zero value.

AM79C975VCW Datasheet(PDF) 192 Page - Advanced Micro Devices

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