AM79C975VCW datasheet(195/304 Pages) AMD

195 / 304 page

Am79C973/Am79C975

195

P R E L I M INARY

ANR1: Status Register (Register 1)

The Status Register identifies the physical and Auto-

negotiation capabilities of the local PHY. This register is

read only; a write will have no effect.

Table 41. ANR1: PHY Status Register (Register 1)

Note:

1. LH = Latching High, LL = Latching Low.

2. The link status bit 2 is fed from register 24 bit 3. Register 24 bit 3 tracks the real time state of the PHY, but link status in ANR1

is latched. After a change of the state of the link, ANR1 must be read twice. The first read will provide old information but it

causes the link status bit to be updated from register 24 bit 3. The second read will then provide the correct state of the link.

Reg

Bits

Name

Description

Read/Write

(Note 1)

Default

Value

100BASE-T4

1 = 100BASE-T4 able,

0 = not 100BASE-T4 able

100BASE-X Full Duplex

1 = 100BASE-X full duplex able,

0 = not 100BASE-X full duplex able

100BASE-X Half Duplex

1 = 100BASE-X half duplex able,

0 = not 100BASE-X half duplex able

10 Mbps Full Duplex

1 = 10 Mbps full duplex able,

0 = not 10 Mbps full duplex able

10 Mbps Half Duplex

1 = 10 Mbps full duplex able,

0 = not 10 Mbps full duplex able

10-7

Reserved

Ignore when read

MF Preamble Suppression

1 = PHY can accept management

(mgmt) frames with or without preamble,

0 = PHY can only accept mgmt frames

with preamble

Auto-Negotiation Complete

1 = Auto-Negotiation completed,

0 = Auto-Negotiation not completed

1 (Note

Remote Fault

1 = remote fault detected,

0 = no remote fault detected

RO, LH

Auto-Negotiation Ability

1 = PHY able to auto-negotiate,

0 = PHY not able to auto-negotiate

1 (Note

2Link Status

1 = link is up,

0 = link is down

RO, LL

Jabber Detect

1 = jabber condition detected,

0 = no jabber condition detected

Extended Capability

1 = extended register capabilities,

0 = basic register set capabilities only

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