AM79C975VCW datasheet(121/304 Pages) AMD

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Am79C973/Am79C975

121

P R E L I M INARY

PCI Power Management Capabilities Register

(PMC)

Offset 42h

Note: All bits of this register are loaded from

EEPROM. The register is aliased to BCR36 for testing

purposes.

Bit

Name

Description

15-11

PME_SPT

PME Support. This 5-bit field indi-

cates the power states in which

the function may assert PME. A

value of 0b for any bit indicates

that the function is not capable of

asserting the PME signal while in

that power state.

Bit(11) XXXX1b - PME can be

asserted from D0.

Bit(12) XXX1Xb - PME can be

asserted from D1.

Bit(13) XX1XXb - PME can be

asserted from D2.

Bit(14) X1XXXb - PME can be

asserted from D3hot.

Bit(15) 1XXXXb - PME can be

asserted from D3cold.

Read only.

Bit 15 of the PMC register indi-

cates that the controller is capa-

ble of generating PME from the

D3 cold state. This capability de-

pends on the presence of auxilia-

ry power, as indicated by the

AUXDET input. The capability

can be disabled by loading a zero

into bit 15 of BCR36 from the EE-

PROM. (This register is aliased to

the PMC register.)

D2_SPT

D2 Support. If this bit is a 1, this

function supports the D2 Power

Management State.

Read only.

D1_SPT

D1 Support. If this bit is a 1, this

function supports the D1 Power

Management State.

Read only.

8-6

RES

Reserved locations. Written as

zeros and read as undefined.

DSI

Device

Specific

Initialization.

When this bit is 1, it indicates that

special initialization of the func-

tion is required (beyond the stan-

dard PCI configuration header)

before the generic class device

driver is able to use it.

Read only.

RES

Reserved locations. Written as

zeros and read as undefined.

PME_CLK

PME Clock. When this bit is a 1,

it indicates that the function relies

on the presence of the PCI clock

for PME operation. When this bit

is a 0 it indicates that no PCI

clock is required for the function

to generate PME.

Functions that do not support

PME generation in any state

must return 0 for this field.

Read only.

2-0

PMIS_VER Power

Management

Interface

Specification Version. A value of

001b indicates that this function

complies with the revision 1.1 of

the PCI Power Management In-

terface Specification.

PCI Power Management Control/Status Register

(PMCSR)

Offset 44h

Bit

Name

Description

PME_STATUS PME Status. This bit is set when

the function would normally as-

sert the PME signal independent

of the state of the PME_EN bit.

Writing a 1 to this bit will clear it

and cause the function to stop as-

serting a PME (if enabled). Writ-

ing a 0 has no effect.

If the function supports PME from

D3cold then this bit is sticky and

must be explicitly cleared by the

operating system each time the

operating system is initially load-

ed.

AM79C975VCW Datasheet(PDF) 121 Page - Advanced Micro Devices

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