AM79C975VCW datasheet(123/304 Pages) AMD

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Am79C973/Am79C975

123

P R E L I M INARY

been selected). Then a second access is performed,

this time to the RDP offset of 10h (for either WIO or

DWIO mode). The RDP access is a read access, and

since RAP has just been loaded with the value of 0004h,

the RDP read will yield the contents of CSR4. A read of

the BDP at this time (offset of 16h when WIO mode has

been selected, 1Ch when DWIO mode has been select-

ed) will yield the contents of BCR4, since the RAP is

used as the pointer into both BDP and RDP space.

RAP: Register Address Port

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-8

RES

Reserved locations. Read and

written as zeros.

7-0

RAP

of these 8 bits determines which

CSR or BCR will be accessed

when an I/O access to the RDP

or BDP port, respectively, is per-

formed.

A write access to undefined CSR

or BCR locations may cause un-

expected reprogramming of the

Am79C973/Am79C975

control

registers. A read access will yield

undefined values.

Read/Write accessible always.

RAP is cleared by H_RESET or

S_RESET and is unaffected by

setting the STOP bit.

Control and Status Registers

The CSR space is accessible by performing accesses

to the RDP (Register Data Port). The particular CSR

that is read or written during an RDP access will depend

upon the current setting of the RAP. RAP serves as a

pointer into the CSR space.

CSR0: Am79C973/Am79C975 Controller Status and

Control Register

Certain bits in CSR0 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR0 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

ERR

Error is set by the OR of CERR,

MISS, and MERR. ERR remains

set as long as any of the error

flags are true.

Read accessible always. ERR is

read only. Write operations are

ignored.

RES

Reserved locations. Read/Write

accessible always. Read returns

zero.

CERR

Collision Error is set by the

Am79C973/Am79C975 controller

when the device operates in half-

duplex mode and the collision in-

puts (10 Mbps) failed to activate

within 20 network bit times after

the chip terminated transmission

(SQE Test). This feature is a

10BASE-T

PHY

test

feature.

CERR reporting is disabled when

the Am79C973/Am79C975 con-

troller

operates

full-duplex

mode.

When the MII port is selected,

CERR is only reported when the

external PHY is operating as a

half-duplex 10BASE-T PHY.

CERR assertion will not result in

an interrupt being generated.

CERR assertion will set the ERR

bit.

Read/Write accessible always.

CERR is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

CERR

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MISS

Missed Frame is set by the

Am79C973/Am79C975 controller

when it has lost an incoming re-

ceive frame resulting from a Re-

ceive

Descriptor

not

being

available. This bit is the only im-

mediate indication that receive

data has been lost since there is

no current receive descriptor.

The

Missed

Frame

Counter

(CSR112) also increments each

time a receive frame is missed.

When MISS is set, INTA is as-

serted if IENA is 1 and the mask

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