AM79C975VCW datasheet(127/304 Pages) AMD

127 / 304 page

Am79C973/Am79C975

127

P R E L I M INARY

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-13

RES

Reserved locations. Read and

written as zero.

MISSM

Missed Frame Mask. If MISSM is

set, the MISS bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

MISSM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

MERRM

Memory Error Mask. If MERRM

is set, the MERR bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

MERRM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

RINTM

Receive Interrupt Mask. If RINTM

is set, the RINT bit will be masked

and unable to set the INTR bit.

Read/Write accessible always.

RINTM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

TINTM

Transmit

Interrupt

Mask.

TINTM is set, the TINT bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

TINTM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

IDONM

Initialization

Done

Mask.

IDONM is set, the IDON bit will be

masked and unable to set the

INTR bit.

Read/Write accessible always.

IDONM is cleared by H_RESET

or S_RESET and is not affected

by STOP.

RES

Reserved location. Read and

written as zeros.

DXSUFLO

Disable Transmit Stop on Under-

flow error.

When DXSUFLO (CSR3, bit 6) is

set to 0, the transmitter is turned

off when an UFLO error occurs

(CSR0, TXON = 0).

When DXSUFLO is set to 1, the

Am79C973/Am79C975 controller

gracefully

recovers

from

UFLO error. It scans the transmit

descriptor ring until it finds the

start of a new frame and starts a

new transmission.

Read/Write accessible always.

DXSUFLO

cleared

H_RESET or S_RESET and is

not affected by STOP.

LAPPEN

Look Ahead Packet Processing

Enable. When set to a 1, the

LAPPEN

bit

will

cause

the

Am79C973/Am79C975 controller

to generate an interrupt following

the descriptor write operation to

the first buffer of a receive frame.

This interrupt will be generated in

addition to the interrupt that is

generated following the descrip-

tor write operation to the last buff-

er of a receive packet. The

interrupt will be signaled through

the RINT bit of CSR0.

Setting LAPPEN to a 1 also en-

ables the Am79C973/Am79C975

controller to read the STP bit of

receive

descriptors.

The

Am79C973/Am79C975 controller

will use the STP information to

determine where it should begin

writing a receive packet’s data.

Note that while in this mode, the

Am79C973/Am79C975 controller

can write intermediate packet

data to buffers whose descriptors

do not contain STP bits set to 1.

Following the write to the last de-

scriptor used by a packet, the

Am79C973/Am79C975 controller

will scan through the next de-

scriptor entries to locate the next

STP bit that is set to a 1. The

Am79C973/Am79C975 controller

will begin writing the next packets

data to the buffer pointed to by

that descriptor.

Note that because several de-

scriptors may be allocated by the

AM79C975VCW Datasheet(PDF) 127 Page - Advanced Micro Devices

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