AM79C975VCW datasheet(131/304 Pages) AMD

131 / 304 page

Am79C973/Am79C975

131

P R E L I M INARY

means that the software can read CSR5 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

TOKINTD

Transmit OK Interrupt Disable. If

TOKINTD is set to 1, the TINT bit

in CSR0 will not be set when a

transmission

was

successful.

Only a transmit error will set the

TINT bit.

TOKINTD has no effect when

LTINTEN (CSR5, bit 14) is set to

1. A transmit descriptor with

LTINT set to 1 will always cause

TINT to be set to 1, independent

of the success of the transmis-

sion.

Read/Write accessible always.

TOKINTD

cleared

H_RESET or S_RESET and is

unaffected by STOP.

LTINTEN

Last Transmit Interrupt Enable.

When set to 1, the LTINTEN bit

will

cause

the

Am79C973/

Am79C975 controller to read bit

28 of TMD1 as LTINT. The set-

ting LTINT will determine if TINT

will be set at the end of the trans-

mission.

Read/Write accessible always.

LTINTEN

cleared

H_RESET or S_RESET and is

unaffected by STOP.

13-12

RES

Reserved locations. Written as

zeros and read as undefined.

SINT

System Interrupt is set by the

Am79C973/Am79C975 controller

when it detects a system error

during a bus master transfer on

the PCI bus. System errors are

data parity error, master abort, or

a target abort. The setting of

SINT due to data parity error is

not dependent on the setting of

PERREN (PCI Command regis-

ter, bit 6).

When SINT is set, INTA is assert-

ed if the enable bit SINTE is 1.

Note that the assertion of an in-

terrupt due to SINT is not depen-

dent on the state of the INEA bit,

since INEA is cleared by the

STOP reset generated by the

system error.

Read/Write accessible always.

SINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect. The state of SINT is not af-

fected by clearing any of the PCI

Status register bits that get set

when

data

parity

error

(DATAPERR, bit 8), master abort

(RMABORT, bit 13), or target

abort (RTABORT, bit 12) occurs.

SINT is cleared by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

SINTE

System Interrupt Enable. If SIN-

TE is set, the SINT bit will be able

to set the INTR bit.

Read/Write accessible always.

SINTE is set to 0 by H_RESET or

S_RESET and is not affected by

setting the STOP bit.

9-8

RES

Reserved locations. Written as

zeros and read as undefined.

EXDINT

Excessive Deferral Interrupt is

set

the

Am79C973/

Am79C975 controller when the

transmitter has experienced Ex-

cessive Deferral on a transmit

frame, where Excessive Deferral

is defined in the ISO 8802-3

(IEEE/ANSI 802.3) standard.

When EXDINT is set, INTA is as-

serted if the enable bit EXDINTE

is 1.

Read/Write accessible always.

EXDINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

EXDINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

EXDINTE

Excessive Deferral Interrupt En-

able. If EXDINTE is set, the

EXDINT bit will be able to set the

INTR bit.

AM79C975VCW Datasheet(PDF) 131 Page - Advanced Micro Devices

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