AM79C975VCW datasheet(135/304 Pages) AMD

135 / 304 page

Am79C973/Am79C975

135

P R E L I M INARY

STINTE

Software Timer Interrupt Enable.

If STINTE is set, the STINT bit

will be able to set the INTR bit.

Read/Write accessible always.

STINTE is set to 0 by H_RESET

and is not affected by S_RESET

or setting the STOP bit

MREINT

PHY Management Read Error In-

terrupt. The PHY Read Error in-

terrupt is set by the Am79C973/

Am79C975 controller to indicate

that the currently read register

from the PHY is invalid. The con-

tents of BCR34 are incorrect and

that the operation should be per-

formed again. The indication of

an incorrect read comes from the

internal PHY.

When MREINT is set to 1, INTA is

asserted if the enable bit MREIN-

TE is set to 1.

Read/Write accessible always.

MREINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MREINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MREINTE

PHY Management Read Error In-

terrupt Enable. If MREINTE is

set, the MREINT bit will be able to

set the INTR bit.

Read/Write accessible always.

MREINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP bit

MAPINT

PHY Management Auto-Poll In-

terrupt. The PHY Auto-Poll inter-

rupt is set by the Am79C973/

Am79C975 controller to indicate

that the currently read status

does not match the stored previ-

ous status indicating a change in

state for the internal PHY. A

change in the Auto-Poll Access

Method (BCR32, Bit 11) will reset

the shadow register and will not

cause an interrupt on the first ac-

cess from the Auto-Poll section.

Subsequent accesses will gener-

ate an interrupt if the shadow reg-

ister

and

the

read

produce differences.

When MAPINT is set to 1, INTA is

asserted if the enable bit MAP-

INTE is set to 1.

Read/Write accessible always.

MAPINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MAPINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MAPINTE

PHY Auto-Poll Interrupt Enable.

If MAPINTE is set, the MAPINT

bit will be able to set the INTR bit.

Read/Write accessible always.

MAPINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP bit

MCCINT

PHY

Management

Command

Complete Interrupt. The PHY

Management Command Com-

plete Interrupt is set by the

Am79C973/Am79C975 controller

when a read or write operation to

the

internal

PHY

Data

Port

(BCR34) is complete.

When MCCINT is set to 1, INTA

is asserted if the enable bit MC-

CINTE is set to 1.

Read/Write accessible always.

MCCINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

MCCINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MCCINTE

PHY

Management

Command

Complete Interrupt Enable. If

MCCINTE is set to 1, the MC-

CINT bit will be able to set the

INTR bit when the host reads or

writes to the internal PHY Data

Port (BCR34) only. Internal PHY

Management Commands will not

generate an interrupt. For in-

stance Auto-Poll state machine

generated management frames

will not generate an interrupt

upon completion unless there is a

compare error which get reported

AM79C975VCW Datasheet(PDF) 135 Page - Advanced Micro Devices

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