AM79C975VCW datasheet(138/304 Pages) AMD

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138

Am79C973/Am79C975

P R E L I M INARY

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

PADR[47:32]Physical

Address

PADR[47:32].The

contents

this register are loaded from EE-

PROM after H_RESET or by an

EEPROM

read

command

(PRGAD, BCR19, bit 14). If the

EEPROM is not present, the con-

tents of this register are unde-

fined.

This register can also be loaded

from the initialization block after

the INIT bit in CSR0 has been set

or a direct register write has been

performed on this register.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR15: Mode

This register’s fields are loaded during the Am79C973/

Am79C975 controller initialization routine with the cor-

responding Initialization Block values, or when a direct

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

PROM

Promiscuous

Mode.

When

PROM = 1, all incoming receive

frames are accepted.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DRCVBC

Disable

Receive

Broadcast.

When

set,

disables

the

Am79C973/Am79C975 controller

from receiving broadcast mes-

sages. Used for protocols that do

not support broadcast address-

ing, except as a function of multi-

cast. DRCVBC is cleared by

activation

H_RESET

S_RESET (broadcast messages

will be received) and is unaffect-

ed by STOP.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DRCVPA

Disable Receive Physical Ad-

dress. When set, the physical ad-

dress detection (Station or node

ID) of the Am79C973/Am79C975

controller

will

disabled.

Frames addressed to the nodes

individual physical address will

not be recognized.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

12-9

RES

Reserved locations. Written as

zeros and read as undefined.

8-7 PORTSEL[1:0] Port Select bits allow for software

controlled selection of the net-

work medium. The only legal val-

ues for this field is 11.

Read/Write accessible only when

either the STOP or the SPND bit

is set. Cleared by H_RESET or

S_RESET and is unaffected by

STOP.

INTL

Internal Loopback. See the de-

scription of LOOP (CSR15, bit 2).

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DRTY

Disable Retry. When DRTY is set

to 1, the Am79C973/Am79C975

controller will attempt only one

transmission. In this mode, the

device will not protect the first 64

bytes of frame data in the Trans-

mit FIFO from being overwritten,

because automatic retransmis-

sion will not be necessary. When

DRTY is set to 0, the Am79C973/

Am79C975 controller will attempt

16 transmissions before signal-

ing a retry error.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

FCOLL

Force Collision. This bit allows

the collision logic to be tested.

The Am79C973/Am79C975 con-

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