AM79C975VCW datasheet(139/304 Pages) AMD

139 / 304 page

Am79C973/Am79C975

139

P R E L I M INARY

troller must be in internal loop-

back for FCOLL to be valid. If

FCOLL = 1, a collision will be

forced during loopback transmis-

sion attempts, which will result in

a Retry Error. If FCOLL = 0, the

Force Collision logic will be dis-

abled. FCOLL is defined after the

initialization block is read.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DXMTFCS

Disable Transmit CRC (FCS).

When DXMTFCS is set to 0, the

transmitter will generate and ap-

pend an FCS to the transmitted

frame. When DXMTFCS is set to

1, no FCS is generated or sent

with

the

transmitted

frame.

DXMTFCS is overridden when

ADD_FCS and ENP bits are set

in TMD1.

When APAD_XMT bit (CSR4,

bit11) is set to 1, the setting of

DXMTFCS has no effect on

frames shorter than 64 bytes.

DXMTFCS

set

and

ADD_FCS is clear for a particular

frame, no FCS will be generated.

If ADD_FCS is set for a particular

frame, the state of DXMTFCS is

ignored and a FCS will be ap-

pended on that frame by the

transmit circuitry. See also the

ADD_FCS bit in TMD1.

This bit was called DTCR in the

LANCE (Am7990) device.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

LOOP

Loopback

Enable

allows

the

Am79C973/Am79C975 controller

to operate in full-duplex mode for

test purposes. The setting of the

full-

duplex control bits in BCR9

have no effect when the device

operates

loopback

mode.

When LOOP = 1, loopback is en-

abled. In combination with INTL

and

MIIILP, various loopback

modes are defined as follows in

Table 24.

Refer to Loop Back Operation

section for more details.

Read/Wr ite acc e ssible on ly

when either the STOP or the

SPND bit is set. LOOP is cleared

by H_RESET or S_RESET and

is unaffected by STOP.

DTX

Disable

Transmit

results

Am79C973/Am79C975 controller

not accessing the Transmit De-

scriptor Ring and, therefore, no

transmissions

are

attempted.

DTX = 0, will set TXON bit (CSR0

bit 4) if STRT (CSR0 bit 1) is as-

serted.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

DRX

Disable Receiver results in the

Am79C973/Am79C975 controller

not accessing the Receive De-

scriptor Ring and, therefore, all

receive frame data are ignored.

DRX = 0,

will

set

RXON

bit

(CSR0 bit 5) if STRT (CSR0 bit 1)

is asserted.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

CSR16: Initialization Block Address Lower

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-0

IADRL

This register is an alias of CSR1.

Read/Write accessible only when

either the STOP or the SPND bit

is set.

Table 24. Loopback Configuration

LOOP

INTL

MIIILP

Function

Normal Operation

Internal Loop

External Loop

AM79C975VCW Datasheet(PDF) 139 Page - Advanced Micro Devices

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