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AM79C975VCW Datasheet(PDF) 141 Page - Advanced Micro Devices |
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AM79C975VCW Datasheet(HTML) 141 Page - Advanced Micro Devices |
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141 / 304 page  Am79C973/Am79C975 141 P R E L I M INARY Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR24: Base Address of Receive Ring Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 BADRL Contains the lower 16 bits of the base address of the Receive Ring. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR25: Base Address of Receive Ring Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 BADRU Contains the upper 16 bits of the base address of the Receive Ring. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR26: Next Receive Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRDAL Contains the lower 16 bits of the next receive descriptor address pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR27: Next Receive Descriptor Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRDAU Contains the upper 16 bits of the next receive descriptor address pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR28: Current Receive Descriptor Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRDAL Contains the lower 16 bits of the current receive descriptor ad- dress pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR29: Current Receive Descriptor Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRDAU Contains the upper 16 bits of the current receive descriptor ad- dress pointer. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR30: Base Address of Transmit Ring Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 BADXL Contains the lower 16 bits of the base address of the Transmit Ring. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected |
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