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AM79C975VCW Datasheet(PDF) 140 Page - Advanced Micro Devices |
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AM79C975VCW Datasheet(HTML) 140 Page - Advanced Micro Devices |
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140 / 304 page  140 Am79C973/Am79C975 P R E L I M INARY CSR17: Initialization Block Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 IADRH This register is an alias of CSR2. Read/Write accessible only when either the STOP or the SPND bit is set. CSR18: Current Receive Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRBAL Contains the lower 16 bits of the current receive buffer address at which the Am79C973/ Am79C975 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR19: Current Receive Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CRBAU Contains the upper 16 bits of the current receive buffer address at which the Am79C973/ Am79C975 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR20: Current Transmit Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CXBAL Contains the lower 16 bits of the current transmit buffer address from which the Am79C973/ Am79C975 controller is transmit- ting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR21: Current Transmit Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 CXBAU Contains the upper 16 bits of the current transmit buffer address from which the Am79C973/ Am79C975 controller is transmit- ting. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR22: Next Receive Buffer Address Lower Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRBAL Contains the lower 16 bits of the next receive buffer address to which the Am79C973/ Am79C975 controller will store incoming frame data. Read/Write accessible only when either the STOP or the SPND bit is set. These bits are unaffected by H_RESET, S_RESET, or STOP. CSR23: Next Receive Buffer Address Upper Bit Name Description 31-16 RES Reserved locations. Written as zeros and read as undefined. 15-0 NRBAU Contains the upper 16 bits of the next receive buffer address to which the Am79C973/ Am79C975 controller will store incoming frame data. |
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