AM79C975VCW datasheet(145/304 Pages) AMD

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Am79C973/Am79C975

145

P R E L I M INARY

H_RESET,

S_RESET,

STOP.

CSR48: Receive Poll Time Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RXPOLL

Receive Poll Time Counter. This

counter is incremented by the

Am79C973/Am79C975 controller

microcode and is used to trigger

the receive descriptor ring polling

operation

the

Am79C973/

Am79C975 controller.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR49: Receive Polling Interval

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RXPOLLINT Receive Polling Interval. This reg-

ister contains the time that the

Am79C973/Am79C975 controller

will wait between successive poll-

ing operations. The RXPOLLINT

value is expressed as the two’s

complement of the desired inter-

val, where each bit of RXPOL-

LINT approximately represents

one clock time period. RXPOL-

LINT[3:0] are ignored. (RXPOL-

LINT[16] is implied to be a 1, so

RXPOLLINT[15]

significant

and does not represent the sign

of the two’s complement RXPOL-

LINT value.)

The default value of this register

is 0000h. This corresponds to a

polling interval of 65,536 clock

periods

(1.966

when

CLK = 33 MHz). The RXPOL-

LINT value of 0000h is created

during the microcode initialization

routine and, therefore, might not

be seen when reading CSR49 af-

ter H_RESET or S_RESET.

If the user desires to program a

value for RXPOLLINT other than

the default, then the correct pro-

cedure is to first set INIT only in

CSR0. Then, when the initializa-

tion sequence is complete, the

user must set STOP (CSR0, bit

2). Then the user may write to

CSR49 and then set STRT in

CSR0. In this way, the default

value of 0000h in CSR47 will be

overwritten with the desired user

value.

If the user does not use the stan-

dard

initialization

procedure

(standard implies use of an initial-

ization block in memory and set-

ting the INIT bit of CSR0), but

instead, chooses to write directly

to each of the registers that are

involved in the INIT operation,

then it is imperative that the user

also writes all zeros to CSR49 as

part of the alternative initialization

sequence.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR58: Software Style

This register is an alias of the location BCR20. Accesses

to and from this register are equivalent to accesses to

BCR20.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-11 RES

Reserved locations. Written as

zeros and read as undefined.

APERREN

Advanced Parity Error Handling

Enable. When APERREN is set

to 1, the BPE bits (RMD1 and

TMD1, bit 23) start having a

meaning. BPE will be set in the

descriptor associated with the

buffer that was accessed when a

data parity error occurred. Note

that since the advanced parity er-

ror handling uses an additional bit

in the descriptor, SWSTYLE (bits

7-0 of this register) must be set to

2 or 3 to program the Am79C973/

AM79C975VCW Datasheet(PDF) 145 Page - Advanced Micro Devices

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