AM79C975VCW datasheet(146/304 Pages) AMD

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146

Am79C973/Am79C975

P R E L I M INARY

Am79C975 controller to use 32-

bit software structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur when

the Am79C973/Am79C975 con-

troller is the target of the transfer.

Read anytime, write accessible

only when either the STOP or the

SPND bit is set. APERREN is

cleared by H_RESET and is not

affected by S_RESET or STOP.

RES

Reserved locations. Written as

zeros and read as undefined.

SSIZE32

Software Size 32 bits. When set,

this

bit

indicates

that

the

Am79C973/Am79C975 controller

utilizes 32-bit software structures

for the initialization block and the

transmit and receive descriptor

entries. When cleared, this bit in-

dicates

that

the

Am79C973/

Am79C975 controller utilizes 16-

bit software structures for the ini-

tialization block and the transmit

and receive descriptor entries. In

this

mode,

the

Am79C973/

Am79C975 controller is back-

wards

compatible

with

the

Am7990 LANCE and Am79C960

PCnet-ISA controllers.

The value of SSIZE32 is deter-

mined

the

Am79C973/

Am79C975 controller according

to the setting of the Software

Style (SWSTYLE, bits 7-0 of this

Read

accessible

always.

SSIZE32 is read only; write oper-

ations will be ignored. SSIZE32

will be cleared after H_RESET

(since SWSTYLE defaults to 0)

and is not affected by S_RESET

or STOP.

If SSIZE32 is reset, then bits

IADR[31:24] of CSR2 will be

used to generate values for the

upper 8 bits of the 32-bit address

bus during master accesses initi-

ated

the

Am79C973/

Am79C975 controller. This action

is required, since the 16-bit soft-

ware structures specified by the

SSIZE32 = 0 setting will yield

only 24 bits of address for the

Am79C973/Am79C975 controller

bus master accesses.

If SSIZE32 is set, then the soft-

ware structures that are common

the

Am79C973/Am79C975

controller and the host system

will supply a full 32 bits for each

address pointer that is needed by

the Am79C973/Am79C975 con-

troller for performing master ac-

cesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE32 bit has no effect on the

defined width for I/O resources.

I/O resource width is determined

by the state of the DWIO bit

(BCR18, bit 7).

7-0

SWSTYLE

Software Style register. The val-

ue in this register determines the

style of register and memory re-

sources that shall be used by the

Am79C973/Am79C975

control-

ler. The Software Style selection

will affect the interpretation of a

few bits within the CSR space,

the order of the descriptor entries

and the width of the descriptors

and initialization block entries.

All Am79C973/Am79C975 con-

troller CSR bits and BCR bits and

all descriptor, buffer, and initial-

ization block entries not cited in

Table 25 are unaffected by the

Software Style selection and are,

therefore, always fully functional

as specified in the CSR and BCR

sections.

Read/Write accessible only when

either the STOP or the SPND bit

is set. The SWSTYLE register will

contain the value 00h following

H_RESET and will be unaffected

by S_RESET or STOP.

AM79C975VCW Datasheet(PDF) 146 Page - Advanced Micro Devices

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