AM79C975VCW datasheet(134/304 Pages) AMD

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134

Am79C973/Am79C975

P R E L I M INARY

and the Am79C973/Am79C975

controller will completely receive

a receive packet if it had already

begun. Additionally, all transmit

packets stored in the transmit

FIFOs and the transmit buffer

area in the SRAM (if one is en-

abled) will be transmitted and all

receive packets stored in the re-

ceive FIFOs, and the receive

buffer area in the SRAM (if one is

enabled) will be transferred into

system memory. Since the FIFO

and SRAM contents are flushed,

it may take much longer before

the Am79C973/Am79C975 con-

troller enters the suspend mode.

The amount of time that it takes

depends on many factors includ-

ing the size of the SRAM, bus la-

tency, and network traffic level.

When a write to CSR5 is per-

formed with bit 0 (SPND) set to 1,

the value that is simultaneously

written to FASTSPNDE is used to

determine which approach

used to enter suspend mode.

Read/Write accessible always.

FASTSPNDE

cleared

H_RESET, S_RESET or by set-

ting the STOP bit.

RXFRTG

Receive Frame Tag. When Re-

ceive Frame Tag is set to 1, a tag

word is put into the receive de-

scriptor supplied by the EADI.

See the section Receive Frame

Tagging for details. This bit is

valid only when the EADISEL

(BCR2, bit 3) is set to 1.

Read/Write accessible always.

RXFRTG

cleared

H_RESET. RXFRTG is unaffect-

ed by S_RESET or by setting the

STOP bit.

RDMD

Receive

Demand,

when

set,

causes the Buffer Management

Unit to access the Receive De-

scriptor Ring without waiting for

the receive poll-time counter to

elapse. If RXON is not enabled,

RDMD has no meaning and no

receive Descriptor Ring access

will occur.

RDMD is required to be set if the

RXDPOLL bit in CSR7 is set. Set-

ting RDMD while RXDPOLL = 0

merely hastens the Am79C973/

Am79C975 controller’s response

to a receive Descriptor Ring En-

try.

Read/Write accessible always.

RDMD is set by writing a 1. Writ-

ing a 0 has no effect. RDMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a re-

ceive

Descriptor.

RDMD

cleared by H_RESET. RDMD is

unaffected by S_RESET or by

setting the STOP bit.

RXDPOLL

Receive Disable Polling. If RXD-

POLL is set, the Buffer Manage-

ment Unit will disable receive

polling. Likewise, if RXDPOLL is

cleared, automatic receive poll-

ing is enabled. If RXDPOLL is

set, RDMD bit in CSR7 must be

set in order to initiate a manual

poll of a receive descriptor. Re-

ceive Descriptor Polling will not

take place if RXON is reset.

Read/Write accessible always.

RXDPOLL

cleared

H_RESET. RXDPOLL is unaf-

fected by S_RESET or by setting

the STOP bit.

STINT

Software Timer Interrupt. The

Software Timer interrupt is set by

the Am79C973/Am79C975 con-

troller when the Software Timer

counts down to 0. The Software

Timer will immediately load the

STVAL (BCR 31, bits 5-0) into the

Software Timer and begin count-

ing down.

When STINT is set to 1, INTA is

asserted if the enable bit STINTE

is set to 1.

Read/Write accessible always.

STINT is cleared by the host by

writing a 1. Writing a 0 has no ef-

fect.

STINT

cleared

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

AM79C975VCW Datasheet(PDF) 134 Page - Advanced Micro Devices

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