AM79C975VCW datasheet(133/304 Pages) AMD

133 / 304 page

Am79C973/Am79C975

133

P R E L I M INARY

In suspend mode, all of the CSR

and BCR registers are accessi-

ble. As long as the Am79C973/

Am79C975 controller is not reset

while

suspend

mode

(by

H_RESET, S_RESET or by set-

ting the STOP bit), no re-initial-

ization of the device is required

after the device comes out of sus-

pend mode. The Am79C973/

Am79C975 controller will contin-

ue at the transmit and receive de-

scriptor

ring

locations,

from

where it had left, when it entered

the suspend mode.

Read/Write accessible always.

SPND is cleared by H_RESET,

S_RESET, or by setting the

STOP bit.

CSR6: RX/TX Descriptor Table Length

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

15-12

TLEN

Contains a copy of the transmit

encoded ring length (TLEN) field

read from the initialization block

during

the

Am79C973/

Am79C975 controller initializa-

tion. This field is written during

the Am79C973/Am79C975 con-

troller initialization routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

TLEN is only defined after initial-

ization. These bits are unaffected

H_RESET,

S_RESET,

STOP.

11-8

RLEN

Contains a copy of the receive

encoded ring length (RLEN) read

from the initialization block during

Am79C973/Am79C975 controller

initialization. This field is written

during

the

Am79C973/

Am79C975 controller initializa-

tion routine.

Read accessible only when either

the STOP or the SPND bit is set.

Write operations have no effect

and should not be performed.

RLEN is only defined after initial-

ization. These bits are unaffected

H_RESET,

S_RESET,

STOP.

7-0

RES

Reserved locations. Read as 0s.

Write operations are ignored.

CSR7: Extended Control and Interrupt 2

Certain bits in CSR7 indicate the cause of an interrupt.

The register is designed so that these indicator bits are

cleared by writing ones to those bit locations. This

means that the software can read CSR7 and write back

the value just read to clear the interrupt condition.

Bit

Name

Description

31-16

RES

Reserved locations. Written as

zeros and read as undefined.

FASTSPNDE

Fast Suspend Enable. When

FASTSPNDE is set to 1, the

Am79C973/Am79C975 controller

performs a fast suspend whenev-

er the SPND bit is set.

When a fast suspend is request-

ed, the Am79C973/Am79C975

controller performs a quick entry

into the suspend mode. At the

time the SPND bit is set, the

Am79C973/Am79C975 controller

will complete the DMA process of

any transmit and/or receive pack-

et that had already begun DMA

activity. In addition, any transmit

packet that had started transmis-

sion will be fully transmitted and

any receive packet that had be-

gun reception will be fully re-

ceived. However, no additional

packets will be transmitted or re-

ceived and no additional transmit

or receive DMA activity will begin.

Hence,

the

Am79C973/

Am79C975 controller may enter

the suspend mode with transmit

and/or receive packets still in the

FIFOs or the SRAM.

When FASTSPNDE is 0 and the

SPND bit is set, the Am79C973/

Am79C975 controller may take

longer before entering the sus-

pend mode. At the time the

SPND bit is set, the Am79C973/

Am79C975 controller will com-

plete the DMA process of a trans-

mit packet if it had already begun

AM79C975VCW Datasheet(PDF) 133 Page - Advanced Micro Devices

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