AM79C975VCW datasheet(132/304 Pages) AMD

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132

Am79C973/Am79C975

P R E L I M INARY

Read/Write accessible always.

EXDINTE

set

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

MPPLBA

Magic Packet Physical Logical

Broadcast Accept. If MPPLBA is

at its default value of 0, the

Am79C973/Am79C975 controller

will only detect a Magic Packet

frame if the destination address

of the packet matches the con-

tent of the physical address regis-

ter (PADR). If MPPLBA is set to

1, the destination address of the

Magic Packet frame can be uni-

cast, multicast, or broadcast.

Note that the setting of MPPLBA

only affects the address detection

of the Magic Packet frame. The

Magic Packet frame’s data se-

quence must be made up of 16

consecutive physical addresses

(PADR[47:0]) regardless of what

kind of destination address it has.

This bit is OR’ed with EMPPLBA

bit (CSR116, bit 6).

Read/Write accessible always.

MPPLBA is set to 0 by H_RESET

or S_RESET and is not affected

by setting the STOP bit.

MPINT

Magic Packet Interrupt. Magic

Packet Interrupt is set by the

Am79C973/Am79C975 controller

when the device is in the Magic

Packet

mode

and

the

Am79C973/Am79C975 controller

receives a Magic Packet frame.

When MPINT is set to 1, INTA is

asserted if IENA (CSR0, bit 6)

and the enable bit MPINTE are

set to 1.

Read/Write accessible always.

MPINT is cleared by the host by

writing a 1. Writing a 0 has no af-

fect.

MPINT

cleared

H_RESET, S_RESET, or by set-

ting the STOP bit.

MPINTE

Magic Packet Interrupt Enable. If

MPINTE is set to 1, the MPINT bit

will be able to set the INTR bit.

Read/Write accessible always.

MPINT

cleared

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

MPEN

Magic Packet Enable. MPEN al-

lows activation of the Magic

Packet mode by the host. The

Am79C973/Am79C975 controller

will enter the Magic Packet mode

when both MPEN and MPMODE

are set to 1.

Read/Write accessible always.

MPEN

cleared

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

MPMODE

The Am79C973/Am79C975 con-

troller will enter the Magic Packet

mode when MPMODE is set to 1

and either PG is asserted or

MPEN is set to 1.

Read/Write accessible always.

MPMODE is cleared to 0 by

H_RESET or S_RESET and is

not affected by setting the STOP

bit

SPND

Suspend. Setting SPND to 1 will

cause

the

Am79C973/

Am79C975 controller to start re-

questing entrance into suspend

mode. The host must poll SPND

until it reads back 1 to determine

that the Am79C973/Am79C975

controller has entered the sus-

pend mode. Setting SPND to 0

will

get

the

Am79C973/

Am79C975 controller out of sus-

pend mode. SPND can only be

set to 1 if STOP (CSR0, bit 2) is

set to 0. H_RESET, S_RESET or

setting the STOP bit will get the

Am79C973/Am79C975 controller

out of suspend mode.

Requesting entrance into the

suspend mode by the host de-

pends on the setting of the

FASTSPNDE bit (CSR7, bit 15).

Refer to the bit description of the

FASTSPNDE bit and the Sus-

pend section in Detailed Func-

tions, Buffer Management Unit

for details.

AM79C975VCW Datasheet(PDF) 132 Page - Advanced Micro Devices

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