| Electronic Components Datasheet Search |
|
AM79C975VCW Datasheet(PDF) 118 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AM79C975VCW Datasheet(HTML) 118 Page - Advanced Micro Devices |
|
118 / 304 page ![]() 118 Am79C973/Am79C975 P R E L I M INARY will drive DEVSEL indicating it will respond to the access. IOBASE is read and written by the host. IOBASE is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. 4-2 IOSIZE I/O size requirements. Read as zeros; write operations have no effect. IOSIZE indicates the size of the I/O space the Am79C973/ Am79C975 controller requires. When the host writes a value of FFFF FFFFh to the I/O Base Ad- dress register, it will read back a value of 0 in bits 4-2. That indi- cates an Am79C973/Am79C975 I/O space requirement of 32 bytes. 1 RES Reserved location. Read as zero; write operations have no effect. 0 IOSPACE I/O space indicator. Read as one; write operations have no effect. Indicating that this base address register describes an I/O base address. PCI Memory Mapped I/O Base Address Register Offset 14h The PCI Memory Mapped I/O Base Address register is a 32-bit register that determines the location of the Am79C973/Am79C975 I/O resources in all of memory space. It is located at offset 14h in the PCI Configuration Space. Bit Name Description 31-5 MEMBASE Memory mapped I/O base ad- dress most significant 27 bits. These bits are written by the host to specify the location of the Am79C973/Am79C975 I/O re- sources in all of memory space. MEMBASE must be written with a valid address before the Am79C973/Am79C975 controller slave memory mapped I/O mode is turned on by setting the ME- MEN bit (PCI Command register, bit 1). When the Am79C973/ Am79C975 controller is enabled for memory mapped I/O mode (MEMEN is set), it monitors the PCI bus for a valid memory com- mand. If the value on AD[31:5] during the address phase of the cycles matches the value of MEMBASE, the Am79C973/ Am79C975 controller will drive DEVSEL indicating it will respond to the access. MEMBASE is read and written by the host. MEMBASE is cleared by H_RESET and is not affected by S_RESET or by setting the STOP bit. 4 MEMSIZE Memory mapped I/O size re- quirements. Read as zeros; write operations have no effect. MEMSIZE indicates the size of the memory space the Am79C973/Am79C975 controller requires. When the host writes a value of FFFF FFFFh to the Memory Mapped I/O Base Ad- dress register, it will read back a value of 0 in bit 4. That indicates a Am79C973/Am79C975 memo- ry space requirement of 32 bytes. 3 PREFETCH Prefetchable. Read as zero; write operations have no effect. Indi- cates that memory space con- trolled by this base address register is not prefetchable. Data in the memory mapped I/O space cannot be prefetched. Because one of the I/O resources in this address space is a Reset regis- ter, the order of the read access- es is important. 2-1 TYPE Memory type indicator. Read as zeros; write operations have no effect. Indicates that this base ad- dress register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. 0 MEMSPACE Memory space indicator. Read as zero; write operations have no effect. Indicates that this base ad- dress register describes a memo- ry base address. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |