AM79C975VCW datasheet(116/304 Pages) AMD

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116

Am79C973/Am79C975

P R E L I M INARY

RMABORT

set

the

Am79C973/Am79C975 controller

and cleared by writing a 1. Writ-

ing a 0 has no effect. RMABORT

is cleared by H_RESET and is

not affected by S_RESET or by

setting the STOP bit.

RTABORT

Received

Target

Abort.

RT-

ABORT is set when a target ter-

minates

Am79C973/

Am79C975 master cycle with a

target abort sequence.

RTABORT

set

the

Am79C973/Am79C975 controller

and cleared by writing a 1. Writ-

ing a 0 has no effect. RTABORT

is cleared by H_RESET and is

not affected by S_RESET or by

setting the STOP bit.

STABORT

Send Target Abort. Read as ze-

ro; write operations have no ef-

fect. The Am79C973/Am79C975

controller will never terminate a

slave access with a target abort

sequence.

STABORT is read only.

10-9

DEVSEL

Device Select Timing. DEVSEL

is set to 01b (medium), which

means

that

the

Am79C973/

Am79C975 controller will assert

DEVSEL two clock periods after

FRAME is asserted.

DEVSEL is read only.

DATAPERR

Data

Parity

Error

Detected.

DATAPERR is set when the

Am79C973/Am79C975 controller

is the current bus master and it

detects a data parity error and the

Parity Error Response enable bit

(PCI Command register, bit 6) is

set.

During the data phase of all

memory read commands, the

Am79C973/Am79C975 controller

checks for parity error by sam-

pling the AD[31:0] and C/BE[3:0]

and the PAR lines. During the

data phase of all memory write

commands,

the

Am79C973/

Am79C975 controller checks the

PERR input to detect whether the

target has reported a parity error.

DATAPERR

set

the

Am79C973/Am79C975 controller

and cleared by writing a 1. Writ-

ing a 0 has no effect. DATAPERR

is cleared by H_RESET and is

not affected by S_RESET or by

setting the STOP bit.

FBTBC

Fast

Back-To-Back

Capable.

Read as one; write operations

have no effect. The Am79C973/

Am79C975 controller is capable

of accepting fast back-to-back

transactions with the first transac-

tion addressing a different target.

6-5

RES

Reserved locations. Read as

zero; write operations have no ef-

fect.

NEW_CAP New Capabilities. This bit indi-

cates whether this function imple-

ments

list

extended

capabilities such as PCI power

management. When set, this bit

indicates the presence of New

Capabilities. A value of 0 means

that this function does not imple-

ment New Capabilities.

Read as one; write operations

have no effect. The Am79C973/

Am79C975 controller supports

the Linked Additional Capabilities

List.

3-0

RES

Reserved locations. Read as

zero; write operations have no ef-

fect.

PCI Revision ID Register

Offset 08h

The PCI Revision ID register is an 8-bit register that

specifies the Am79C973/Am79C975 controller revision

number. The value of this register is 4Xh with the lower

four bits being silicon-revision dependent.

The PCI Revision ID register is located at offset 08h in

the PCI Configuration Space. It is read only.

PCI Programming Interface Register

Offset 09h

The PCI Programming Interface register is an 8-bit reg-

ister that identifies the programming interface of

Am79C973/Am79C975 controller. PCI does not define

AM79C975VCW Datasheet(PDF) 116 Page - Advanced Micro Devices

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