AM79C975VCW datasheet(114/304 Pages) AMD

114 / 304 page

114

Am79C973/Am79C975

P R E L I M INARY

ler within AMD’s product line. The Am79C973/

Am79C975 Device ID is 2000h. Note that this Device

ID is not the same as the Part number in CSR88 and

CSR89. The Device ID is assigned by AMD. The De-

vice ID is the same as the PCnet-PCI II (Am79C970A)

and PCnet-FAST (Am79C971) devices.

The PCI Device ID register is located at offset 02h in

the PCI Configuration Space. It is read only.

PCI Command Register

Offset 04h

The PCI Command register is a 16-bit register used to

control the gross functionality of the Am79C973/

Am79C975 controller. It controls the Am79C973/

Am79C975 controller’s ability to generate and respond

to PCI bus cycles. To logically disconne ct th e

Am79C973/Am79C975 device from all PCI bus cycles

except configuration cycles, a value of 0 should be writ-

ten to this register.

The PCI Command register is located at offset 04h in

the PCI Configuration Space. It is read and written by

the host.

Bit

Name

Description

15-10

RES

Reserved locations. Read as ze-

ros; write operations have no ef-

fect.

FBTBEN

Fast Back-to-Back Enable. Read

as zero; write operations have no

effect.

The

Am79C973/

Am79C975 controller will not

generate Fast Back-to-Back cy-

cles.

SERREN

SERR Enable. Controls the as-

sertion of the SERR pin. SERR is

disabled

when

SERREN

cleared. SERR will be asserted

on detection of an address parity

error and if both SERREN and

PERREN (bit 6 of this register)

are set.

SERREN

cleared

H_RESET and is not effected by

S_RESET or by setting the STOP

bit.

RES

Reserved location. Read as ze-

ros; write operations have no ef-

fect.

PERREN

Parity Error Response Enable.

Enables the parity error response

functions. When PERREN is 0

and the Am79C973/Am79C975

controller detects a parity error, it

only sets the Detected Parity Er-

ror bit in the PCI Status register.

When

PERREN

the

Am79C973/Am79C975 controller

asserts PERR on the detection of

a data parity error. It also sets the

DATAPERR bit (PCI Status reg-

ister, bit 8), when the data parity

error occurred during a master

cycle. PERREN also enables re-

porting

address

parity

errors

through the SERR pin and the

SERR bit in the PCI Status regis-

ter.

PERREN

cleared

H_RESET and is not affected by

S_RESET or by setting the STOP

bit.

VGASNOOP

VGA Palette Snoop. Read as ze-

ro; write operations have no ef-

fect.

MWIEN

Memory Write and Invalidate Cy-

cle Enable. Read as zero; write

operations have no effect. The

Am79C973/Am79C975 controller

only generates Memory Write cy-

cles.

SCYCEN

Special Cycle Enable. Read as

zero; write operations have no ef-

fect. The Am79C973/Am79C975

controller ignores all Special Cy-

cle operations.

BMEN

Bus

Master

Enable.

Setting

BMEN enables the Am79C973/

Am79C975 controller to become

a bus master on the PCI bus. The

host must set BMEN before set-

ting the INIT or STRT bit in CSR0

the

Am79C973/Am79C975

controller.

BMEN is cleared by H_RESET

and is not effected by S_RESET

or by setting the STOP bit.

MEMEN

Memory Space Access Enable.

The Am79C973/Am79C975 con-

troller will ignore all memory ac-

cesses when MEMEN is cleared.

The host must set MEMEN be-

fore the first memory access to

the device.

AM79C975VCW Datasheet(PDF) 114 Page - Advanced Micro Devices

AM79C975VCW Datasheet(HTML) 114 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL