A29400 Series

PRELIMINARY

(February, 2001, Version 0.1)

28

AMIC Technology, Inc.

Addresses

WE

OE

CE

Data

555 for program

2AA for erase

PA

Data Polling

Note :

2. Figure indicates the last two bus cycles of the command sequence.

PD for program

30 for sector erase

10 for chip erase

PA for program

SA for sector erase

555 for chip erase

A0 for program

55 for erase

RESET

RY/BY

Erase and Programming Performance

Parameter

Typ. (Note 1)

Max. (Note 2)

Unit

Comments

Sector Erase Time

1.0

8

sec

Chip Erase Time

11

sec

Excludes 00h programming

prior to erasure

Byte Programming Time

35

300

µs

Word Programming Time

12

500

µs

Byte Mode

3.6

10.8

sec

Chip Programming Time

(Note 3)

Word Mode

3.1

9.3

sec

Excludes system-level

overhead (Note 5)

Notes:

1. Typical program and erase times assume the following conditions: 25

°C, 5.0V VCC, 10,000 cycles. Additionally,

programming typically assumes checkerboard pattern.

2. Under worst case conditions of 90

°C, VCC = 4.5V (4.75V for -55), 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most

bytes program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded,

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See

Table 4 for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 10,000 cycles.