EP2C8 datasheet(101/168 Pages) ALTERA

101 / 168 page

Altera Corporation

5–11

February 2008

Cyclone II Device Handbook, Volume 1

DC Characteristics and Timing Specifications

Characteristics

for Different Pin

Types

Table 5–10 shows the types of pins that support bus hold circuitry.

Differential 1.8-V

HSTL class I

and II (3)

———

—

VCCIO

– 0.4

——

0.4

Differential

SSTL-2 class I

(4)

———

—

VTT +

0.57

——

VTT –

0.57

Differential

SSTL-2 class II

(4)

———

—

VTT +

0.76

——

VTT –

0.76

Differential

SSTL-18 class I

(4)

—

0.5 ×

VCCIO

–

0.125

0.5 ×

VCCIO

0.5 ×

VCCIO

0.125

VTT +

0.475

——

VTT –

0.475

Differential

SSTL-18 class II

(4)

—

0.5 ×

VCCIO

–

0.125

0.5 ×

VCCIO

0.5 ×

VCCIO

0.125

VCCIO

– 0.28

—

0.28

Notes to Table 5–9:

(1)

The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output

pins.

(2)

The RSDS and mini-LVDS I/O standards are only supported on output pins.

(3)

The differential 1.8-V HSTL and differential 1.5-V HSTL I/O standards are only supported on clock input pins and

PLL output clock pins.

(4)

The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock

pins.

Table 5–9. DC Characteristics for User I/O Pins Using Differential I/O Standards Note (1) (Part 2 of 2)

I/O Standard

VOD (mV)

ΔVOD (mV)

VOCM (V)

VOH (V)

VOL (V)

Min

Typ

Max

Min Max

Min

Typ

Max

Min

Max

Min

Max

Table 5–10. Bus Hold Support

Pin Type

Bus Hold

I/O pins using single-ended I/O standards

Yes

I/O pins using differential I/O standards

Dedicated clock pins

JTAG

Configuration pins

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