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EP2C8 Datasheet(PDF) 103 Page - Altera Corporation |
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EP2C8 Datasheet(HTML) 103 Page - Altera Corporation |
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103 / 168 page ![]() Altera Corporation 5–13 February 2008 Cyclone II Device Handbook, Volume 1 DC Characteristics and Timing Specifications Table 5–13 shows the Cyclone II device pin capacitance for different I/O pin types. Power Consumption You can calculate the power usage for your design using the PowerPlay Early Power Estimator and the PowerPlay Power Analyzer feature in the Quartus® II software. The interactive PowerPlay Early Power Estimator is typically used during the early stages of FPGA design, prior to finalizing the project, to get a magnitude estimate of the device power. The Quartus II software PowerPlay Power Analyzer feature is typically used during the later stages of FPGA design. The PowerPlay Power Analyzer also allows you to apply test vectors against your design for more accurate power consumption modeling. In both cases, only use these calculations as an estimation of power, not as a specification. For more information on PowerPlay tools, refer to the PowerPlay Early Power Estimator User Guide and the Power Estimation and Analysis section in volume 3 of the Quartus II Handbook. 1 You can obtain the Excel-based PowerPlay Early Power Estimator at www.altera.com. Refer to Table 5–3 on page 5–3 for typical ICC standby specifications. The power-up current required by Cyclone II devices does not exceed the maximum static current. The rate at which the current increases is a function of the system power supply. The exact amount of current consumed varies according to the process, temperature, and power ramp rate. The duration of the ICCINT power-up requirement depends on the VCCINT voltage supply rise time. Table 5–13. Device Capacitance Note (1) Symbol Parameter Typical Unit CIO Input capacitance for user I/O pin. 6 pF CLVDS Input capacitance for dual-purpose LVDS/user I/O pin. 6 pF CVREF Input capacitance for dual-purpose VREF pin when used as VREF or user I/O pin. 21 pF CCLK Input capacitance for clock pin. 5 pF Note to Table 5–13: (1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflectometry (TDR). Measurement accuracy is within ±0.5 pF. |
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