EP2C8 datasheet(108/168 Pages) ALTERA

108 / 168 page

5–18

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2008

Timing Specifications

Internal Timing

Refer to Tables 5–16 through 5–19 for the internal timing parameters.

Larger

Designs

8-bit, 1024 pt, Quad Output,

4 Parallel FFT Engines, Buffered

Burst, 3 Mults/5 Adders FFT

function

8053

200.0

195.0

149.23

163.02

8-bit, 1024 pt, Quad Output,

4 Parallel FFT Engines, Buffered

Burst, 4 Mults/2 Adders FFT

function

7453

200.0

195.0

151.28

163.02

Notes to Table 5–15 :

(1)

This application uses registered inputs and outputs.

(2)

This application uses registered multiplier input and output stages within the DSP block.

(3)

This application uses the same clock source for both A and B ports.

(4)

This application uses independent clock sources for A and B ports.

(5)

This application uses PLL clock outputs that are globally routed to connect and drive M4K clock ports. Use of

non-PLL clock sources or local routing to drive M4K clock ports may result in lower performance numbers than

shown here. Refer to the Quartus II timing report for actual performance numbers.

(6)

These numbers are for commercial devices.

(7)

These numbers are for automotive devices.

Table 5–15. Cyclone II Performance (Part 4 of 4)

Applications

Resources Used

Performance (MHz)

LEs

M4K

Memory

Blocks

DSP

Blocks

–6

Speed

Grade

–7

Speed

Grade

(6)

–7

Speed

Grade

(7)

–8

Speed

Grade

Table 5–16. LE_FF Internal Timing Microparameters (Part 1 of 2)

Parameter

–6 Speed Grade (1)

–7 Speed Grade (2)

–8 Speed Grade (3)

Unit

Min

Max

Min

Max

Min

Max

TSU

–36

—

–40

—

–40

—

–38

—

–40

—

266

—

306

—

306

—

286

—

306

—

TCO

141

250

135

277

135

304

—

141

—

141

—

TCLR

191

—

244

—

244

—

217

—

244

—

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