PCI2060 datasheet(49/76 Pages) TI

49 / 76 page

Configuration Header Space

April 2005

SCPS096A

4.11 Header Type Register (0Eh)

The header type register is read-only and returns 01h when read, indicating that the PCI2060 configuration

space adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes 10h–3Fh of the configuration

space is considered.

Bit Number

Reset State

4.12 BIST Register (0Fh)

The PCI2060 bridge does not support built-in self-test (BIST). The BIST register is read-only and returns the

value 00h when read.

Bit Number

Reset State

4.13 Primary Bus Number Register (18h)

The primary bus number register indicates the primary bus number to which the PCI2060 bridge is connected.

The bridge uses this register, in conjunction with the secondary bus number and subordinate bus number

registers, to decode type 1 configuration transactions on the secondary interface that must be either converted

to special cycle transactions on the primary interface or passed upstream unaltered.

Bit Number

Reset State

4.14 Secondary Bus Number Register (19h)

This read/write register specifies the bus number of the PCI bus segment that the secondary interface is

connected to. The PCI2060 bridge uses this register to determine when to respond to and forward type 1

configuration transactions on the primary interface, and to determine when to convert them to type 0 or special

cycle transactions on the secondary interface.

Bit Number

Reset State

4.15 Subordinate Bus Number Register (1Ah)

This read/write register specifies the bus number of the highest number PCI bus segment that is subordinate

to the PCI2060 bridge. In conjunction with the secondary bus number register, the PCI2060 bridge uses this

them to the secondary interface as a type 1 configuration transaction.

Bit Number

Reset State

4.16 Secondary Latency Timer Register (1Bh)

This read/write register defines the minimum period of time (in PCI clock cycles since S_FRAME is asserted)

that the PCI2060 bridge may continue a burst transaction even if it is preempted (the PCI2060 secondary bus

grant is deasserted). When this register is set to 00h, the PCI2060 bridge relinquishes the bus after the first

data transfer when its secondary bus grant is deasserted.

Bit Number

Reset State

PCI2060 Datasheet(PDF) 49 Page - Texas Instruments