PCI2060 datasheet(71/76 Pages) TI

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Electrical Characteristics

April 2005

SCPS096A

6.5

66-MHz PCI Signal Timing

NOTE: Vtest = 1.5 V for 5-V signals; 0.4 VCC for 3.3-V signals

Valid

Vtest

t(inval)

ton

toff

tsu

CLK

Output

Input

Figure 6−2. PCI Signal Timing Measurement Conditions

PARAMETER

MIN

MAX

UNIT

tv(bus)

CLK to signal valid delay—bused signals (see Notes 4, 5, and 6)

tv(ptp)

CLK to signal valid delay—point-to-point (see Notes 4, 5, and 6)

ton

Float to active delay (see Notes 4, 5, and 6)

toff

Active to float delay (see Notes 4, 5, and 6)

tsu(bus)

Input setup time to CLK—bused signal (see Notes 4, 5, and 6)

tsu(ptp)

Input setup time to CLK—point-to-point (see Notes 4, 5, and 6)

Input signal hold time from CLK (see Notes 4 and 5)

NOTES:

4. See Figure 6−2

5. All primary interface signals are synchronized to P_CLK and all secondary interface signals are synchronized to S_CLK.

6. Bused signals are as follows:

P_AD, P_C/BE, P_PAR, P_PERR, P_SERR, P_FRAME, P_IRDY, P_TRDY, P_LOCK, P_DEVSEL, P_STOP, P_IDSEL, S_AD,

S_C/BE, S_PAR, S_PERR, S_SERR, S_FRAME, S_IRDY, S_TRDY, S_LOCK, S_DEVSEL, S_STOP

Point-to-point signals are as follows:

P_REQ, S_REQx, P_GNT, S_GNTx

PCI2060 Datasheet(PDF) 71 Page - Texas Instruments